On Fri, 28 Jul 2023 14:13:54 +0100, daire.mcnamara@xxxxxxxxxxxxx wrote: > This patch series contains fixes and clean-ups for the Microchip PolarFire SoC PCIe driver > > These patches are extracted from the link below to separate them from the outbound and inbound > range handling which is taking considerable time. > Link: https://lore.kernel.org/linux-riscv/20230111125323.1911373-1-daire.mcnamara@xxxxxxxxxxxxx/ > > Resending with correct e-mail address list > > [...] Applied to controller/microchip, thanks! [1/7] PCI: microchip: Correct the DED and SEC interrupt bit offsets https://git.kernel.org/pci/pci/c/6d473a5a2613 [2/7] PCI: microchip: Enable building driver as a module https://git.kernel.org/pci/pci/c/2e245bc8a2ab [3/7] PCI: microchip: Align register, offset, and mask names with hw docs https://git.kernel.org/pci/pci/c/4d6bf4c49578 [4/7] PCI: microchip: Enable event handlers to access bridge and ctrl ptrs https://git.kernel.org/pci/pci/c/d1d6a0c9e79c [5/7] PCI: microchip: Clean up initialisation of interrupts https://git.kernel.org/pci/pci/c/4f0b91247f78 [6/7] PCI: microchip: Gather MSI information from hardware config registers https://git.kernel.org/pci/pci/c/1abb722888fd [7/7] PCI: microchip: Re-partition code between probe() and init() https://git.kernel.org/pci/pci/c/bac406c34fbc Thanks, Lorenzo
