On Fri, Jun 23, 2023 at 10:40:56AM -0400, Jim Quinlan wrote:
> During long periods of the PCIe RC HW being in an L1SS sleep state, there
> may be a timeout on an internal bus access, even though there may not be
> any PCIe access involved. Such a timeout will cause a subsequent CPU
> abort.
>
> So, when "brcm,enable-l1ss" is observed, we increase the timeout value to
> four seconds instead of using its HW default.
>
> Signed-off-by: Jim Quinlan <james.quinlan@xxxxxxxxxxxx>
> Tested-by: Florian Fainelli <f.fainelli@xxxxxxxxx>
> ---
> drivers/pci/controller/pcie-brcmstb.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index d30636a725d7..fe0415a98c63 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -1034,6 +1034,21 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> return 0;
> }
>
> +/*
> + * This extends the timeout period for an access to an internal bus. This
> + * access timeout may occur during L1SS sleep periods even without the
> + * presence of a PCIe access.
> + */
> +static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
> +{
> + /* TIMEOUT register is two registers before RGR1_SW_INIT_1 */
> + const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;
Nit: you could define an offset for the TIMEOUT register, if that makes
it any cleaner, up to you.
> + u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */
It would be useful to describe why this has to be 4 seconds in case
someone in the future will have to change it.
Thanks,
Lorenzo
> + /* Each unit in timeout register is 1/216,000,000 seconds */
> + writel(216 * timeout_us, pcie->base + REG_OFFSET);
> +}
> +
> static void brcm_config_clkreq(struct brcm_pcie *pcie)
> {
> bool l1ss = of_property_read_bool(pcie->np, "brcm,enable-l1ss");
> @@ -1059,6 +1074,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie)
> * of 400ns, as specified in 3.2.5.2.2 of the PCI Express
> * Mini CEM 2.0 specification.
> */
> + brcm_extend_rbus_timeout(pcie);
> clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK;
> dev_info(pcie->dev, "bi-dir CLKREQ# for L1SS power savings");
> } else {
> --
> 2.17.1
>
