On 7/19/23 12:23 PM, Smita Koralahalli wrote:
> According to Section 9.17.2, Table 9-26 of CXL Specification [1], owner
> of AER should also own CXL Protocol Error Management as there is no
> explicit control of CXL Protocol error. And the CXL RAS Cap registers
> reported on Protocol errors should check for AER _OSC rather than CXL
> Memory Error Reporting Control _OSC.
>
> The CXL Memory Error Reporting Control _OSC specifically highlights
> handling Memory Error Logging and Signaling Enhancements. These kinds of
> errors are reported through a device's mailbox and can be managed
> independently from CXL Protocol Errors.
Does it fix any issue? If yes, please include that in the commit log.
Since you are removing some change, maybe it needs Fixes: tag?
>
> [1] Compute Express Link (CXL) Specification, Revision 3.1, Aug 1 2022.
>
> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@xxxxxxx>
> ---
> drivers/cxl/pci.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 1cb1494c28fe..44a21ab7add5 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -529,7 +529,6 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
>
> static int cxl_pci_ras_unmask(struct pci_dev *pdev)
> {
> - struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus);
> struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
> void __iomem *addr;
> u32 orig_val, val, mask;
> @@ -541,9 +540,9 @@ static int cxl_pci_ras_unmask(struct pci_dev *pdev)
> return 0;
> }
>
> - /* BIOS has CXL error control */
> - if (!host_bridge->native_cxl_error)
> - return -ENXIO;
> + /* BIOS has PCIe AER error control */
> + if (!pcie_aer_is_native(pdev))
> + return 0;
>
> rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap);
> if (rc)
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer
