Hi Liviu,
On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote:
> On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> > Add both PCIe3 controllers together with the shared PHY.
> >
> > Signed-off-by: Sebastian Reichel <sebastian.reichel@xxxxxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
> > 1 file changed, 120 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > index 88d702575db2..8f210f002fac 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > @@ -7,6 +7,11 @@
> > #include "rk3588-pinctrl.dtsi"
> >
> > / {
> > + pcie30_phy_grf: syscon@fd5b8000 {
> > + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
> > + reg = <0x0 0xfd5b8000 0x0 0x10000>;
> > + };
> > +
> > pipe_phy1_grf: syscon@fd5c0000 {
> > compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> > reg = <0x0 0xfd5c0000 0x0 0x100>;
>
> What tree is based this on? Even after applying your PCIe2 series I don't have the above
> node so the patch doesn't apply to mainline.
You are missing naneng-combphy support:
https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708
-- Sebastian
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