On Mon, Jul 17, 2023 at 08:45:14AM -0600, Rob Herring wrote:
> On Thu, Jun 15, 2023 at 10:41 AM Frank Li <Frank.Li@xxxxxxx> wrote:
> >
> > From: Xiaowei Bao <xiaowei.bao@xxxxxxx>
> >
> > A workaround for the issue where the PCI Express Endpoint (EP) controller
> > loses the values of the Maximum Link Width and Supported Link Speed from
> > the Link Capabilities Register, which initially configured by the Reset
> > Configuration Word (RCW) during a link-down or hot reset event.
>
> What makes this Layerscape specific? Seems like something internal to DWC.
layerscape designed behavor is that LINK speed and width controled by RCW.
But design have been 'defect' when switch to dwc controller, may not
correct connect some wire. So provide an errata, ask software recover such
information when link up/down to align design spec.
For example, RCW config max link is 2lan, after link down/up, DWC reset
to max link to 4lan. So host side get a report, max link is 4 lan.
It will not impact function, just information miss matched.
Frank
>
> >
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@xxxxxxx>
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>
> > Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
> > ---
> > drivers/pci/controller/dwc/pci-layerscape-ep.c | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > index 4e4fdd1dfea7..2ef02d827eeb 100644
> > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > @@ -45,6 +45,7 @@ struct ls_pcie_ep {
> > struct pci_epc_features *ls_epc;
> > const struct ls_pcie_ep_drvdata *drvdata;
> > int irq;
> > + u32 lnkcap;
> > bool big_endian;
> > };
> >
> > @@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
> > struct ls_pcie_ep *pcie = dev_id;
> > struct dw_pcie *pci = pcie->pci;
> > u32 val, cfg;
> > + u8 offset;
> >
> > val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR);
> > ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);
> > @@ -81,6 +83,13 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
> > return IRQ_NONE;
> >
> > if (val & PEX_PF0_PME_MES_DR_LUD) {
> > +
> > + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > +
> > + dw_pcie_dbi_ro_wr_en(pci);
> > + dw_pcie_writew_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap);
> > + dw_pcie_dbi_ro_wr_dis(pci);
> > +
> > cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG);
> > cfg |= PEX_PF0_CFG_READY;
> > ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg);
> > @@ -216,6 +225,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
> > struct ls_pcie_ep *pcie;
> > struct pci_epc_features *ls_epc;
> > struct resource *dbi_base;
> > + u8 offset;
> > int ret;
> >
> > pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> > @@ -252,6 +262,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
> >
> > platform_set_drvdata(pdev, pcie);
> >
> > + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > + pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> > +
> > ret = dw_pcie_ep_init(&pci->ep);
> > if (ret)
> > return ret;
> > --
> > 2.34.1
> >
