Re: [PATCH v7 2/2] PCI: Don't put non-power manageable PCIe root ports into D3

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On Wed, Jul 12, 2023 at 01:48:11PM +0200, Rafael J. Wysocki wrote:
> On Wed, Jul 12, 2023 at 12:14 AM Bjorn Helgaas <helgaas@xxxxxxxxxx> wrote:
> > On Mon, Jul 10, 2023 at 07:53:25PM -0500, Mario Limonciello wrote:


> > Tangent unrelated to *this* patch: I don't know how to think about the
> > pci_use_mid_pm() in platform_pci_power_manageable() because I haven't
> > seen a MID spec.  pci_use_mid_pm() isn't dependent on "dev", so we
> > claim *all* PCI devices, even external ones, are power manageable by
> > the platform, which doesn't seem right.
> No, we don't.
> This only means that PCI devices may be power manageable by the
> platform and so the platform code should be invoked to check that.
> AFAICS, intel_mid_pwr_get_lss_id(() will return an error for a device
> without platform PM support.

If it's a problem somewhere, we may even harden that by checking
the bus nr to be 0. The devices outside bus 0 for sure have not to
be affected by this code.

With Best Regards,
Andy Shevchenko

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