Hi All,
A gentle ping.
Thanks,
KC
On 6/30/2023 9:55 AM, Krishna chaitanya chundru wrote:
Add basic support for managing "pcie-mem" interconnect path by setting
a low constraint before enabling clocks and updating it after the link
is up based on link speed and width the device got enumerated.
chnages from v6:
- addressed the comments as suggested by mani.
changes from v5:
- addressed the comments by mani.
changes from v4:
- rebased with linux-next.
- Added comments as suggested by mani.
- removed the arm: dts: qcom: sdx55: Add interconnect path
as that patch is already applied.
changes from v3:
- ran make DT_CHECKER_FLAGS=-m dt_binding_check and fixed
errors.
- Added macros in the qcom ep driver patch as suggested by Dmitry
changes from v2:
- changed the logic for getting speed and width as suggested
by bjorn.
- fixed compilation errors.
Krishna chaitanya chundru (3):
dt-bindings: PCI: qcom: ep: Add interconnects path
arm: dts: qcom: sdx65: Add PCIe interconnect path
PCI: qcom-ep: Add ICC bandwidth voting support
.../devicetree/bindings/pci/qcom,pcie-ep.yaml | 13 ++++
arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 3 +
drivers/pci/controller/dwc/pcie-qcom-ep.c | 71 ++++++++++++++++++++++
3 files changed, 87 insertions(+)
