On 7/3/2023 7:19 PM, Li Chen wrote:
Hi Achal,
---- On Mon, 03 Jul 2023 19:29:14 +0800 Achal Verma wrote ---
> As per the PCIe Card Electromechanical specification REV. 3.0, PERST#
> signal should be de-asserted after minimum 100ms from the time power-rails
> become stable. Current delay of 100us is observed to be not enough on some
> custom platform implemented using TI's K3 SOCs.
>
> So, to ensure 100ms delay to give sufficient time for power-rails and
> refclk to become stable, change delay from 100us to 100ms.
What problems could arise if the delay is too small? Would some endpoints not be able to detect it?
If delay is small, cpu stall is reported during probe() while accessing
PCIe registers in some cases.
Regards,
Li
