On 7/3/23 17:58, Rick Wertenbroek wrote:
> A 32-bit mask was used on the 64-bit PCI address used for mapping MSIs.
> This would result in the upper 32 bits being unintentionally zeroed and
> MSIs getting mapped to incorrect PCI addresses if the address had any
> of the upper bits set.
>
> Replace 32-bit mask by appropriate 64-bit mask.
>
> Fixes: dc73ed0f1b8b ("PCI: rockchip: Fix window mapping and address translation for endpoint")
> Reported-by: Dan Carpenter <dan.carpenter@xxxxxxxxxx>
> Closes: https://lore.kernel.org/linux-pci/8d19e5b7-8fa0-44a4-90e2-9bb06f5eb694@moroto.mountain/
> Signed-off-by: Rick Wertenbroek <rick.wertenbroek@xxxxxxxxx>
> Cc: stable@xxxxxxxxxxxxxxx
Looks good to me.
Reviewed-by: Damien Le Moal <dlemoal@xxxxxxxxxx>
> ---
> drivers/pci/controller/pcie-rockchip.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
> index fe0333778fd9..627d08b34827 100644
> --- a/drivers/pci/controller/pcie-rockchip.h
> +++ b/drivers/pci/controller/pcie-rockchip.h
> @@ -158,7 +158,9 @@
> #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
> #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)
>
> -#define PCIE_ADDR_MASK 0xffffff00
> +#define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
> +#define MIN_AXI_ADDR_BITS_PASSED 8
> +#define PCIE_ADDR_MASK GENMASK(63, MIN_AXI_ADDR_BITS_PASSED)
> #define PCIE_CORE_AXI_CONF_BASE 0xc00000
> #define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
> #define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
> @@ -185,8 +187,6 @@
> #define AXI_WRAPPER_TYPE1_CFG 0xb
> #define AXI_WRAPPER_NOR_MSG 0xc
>
> -#define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
> -#define MIN_AXI_ADDR_BITS_PASSED 8
> #define PCIE_RC_SEND_PME_OFF 0x11960
> #define ROCKCHIP_VENDOR_ID 0x1d87
> #define PCIE_LINK_IS_L2(x) \
--
Damien Le Moal
Western Digital Research
