On 23.06.2023 06:57, Devi Priya wrote: > Configure the ADDR_BIT_INDEX of PARF_AXI_MSTR_WR_ADDR_HALT_V2 register with > 0x1E to increase the halt window size to 1GB so that, when new inbound > posted write transactions whose address crosses 1G address range, the > controller would halt all the incoming writes until all the previous AXI > responses are received. > > Signed-off-by: Devi Priya <quic_devipriy@xxxxxxxxxxx> > --- Has this been tested on anything except IPQ9574? Does it concern other SoCs? > This patch depends on the below series which adds support for PCIe > controllers in IPQ9574 > https://lore.kernel.org/linux-arm-msm/20230519090219.15925-1-quic_devipriy@xxxxxxxxxxx/ > > drivers/pci/controller/dwc/pcie-qcom.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index c7579dfa5b1c..26c40e006120 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -116,6 +116,8 @@ > > /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */ > #define EN BIT(31) > +#define ADDR_BIT_INDEX (BIT(0) | BIT(1) | BIT(2) | \ > + BIT(3) | BIT(4) | BIT(5)) You surely should have the names of these bitfields, mind defining them? > > /* PARF_LTSSM register fields */ > #define LTSSM_EN BIT(8) > @@ -154,6 +156,8 @@ > > #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) > > +#define PARF_AXI_MSTR_WR_ADDR_HALT_WINDOW_SIZE 0x1e > + > #define QCOM_PCIE_1_0_0_MAX_CLOCKS 4 > struct qcom_pcie_resources_1_0_0 { > struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS]; > @@ -1126,6 +1130,11 @@ static int qcom_pcie_post_init(struct qcom_pcie *pcie) > > writel(0, pcie->parf + PARF_Q2A_FLUSH); > > + val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); > + val &= ~ADDR_BIT_INDEX; > + writel(val | PARF_AXI_MSTR_WR_ADDR_HALT_WINDOW_SIZE, pcie->parf + > + PARF_AXI_MSTR_WR_ADDR_HALT_V2); val |= .. writel(val, pcie..) would be more readable Konrad > + > dw_pcie_dbi_ro_wr_en(pci); > writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); >
