Hello Serge,
> From: Serge Semin, Sent: Monday, June 5, 2023 7:53 PM
>
> On Wed, May 10, 2023 at 03:22:22PM +0900, Yoshihiro Shimoda wrote:
> > To improve code readability, modify PCIE_PORT_LINK_CONTROL handling.
>
> So basically you are doing the same update as in the Patch 9:
> detaching the already implemented link width setups into a separate
> method. Why do you split them up into the incremental updates?
I thought that splitting them was review-friendly. But, it's wrong...
> Just
> squash this patch into the patch 9. The resultant patch would be an
> atomic update and a preparation before adding the PCI_EXP_LNKCAP field
> update. The later would lead to the fully coherent maximum link width
> setup method in accordance with the DW PCIe hardware manual.
I got it.
Best regards,
Yoshihiro Shimoda
> -Serge(y)
>
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> > ---
> > drivers/pci/controller/dwc/pcie-designware.c | 40 +++++++-------------
> > 1 file changed, 13 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index 68aefbbcd68c..5dc423dd2f21 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -721,28 +721,40 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> >
> > static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > {
> > - u32 lwsc;
> > + u32 lwsc, plc;
> >
> > if (!num_lanes)
> > return;
> >
> > + /* Set the number of lanes */
> > + plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
> > + plc &= ~PORT_LINK_MODE_MASK;
> > +
> > /* Set link width speed control register */
> > lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> > lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK;
> > switch (num_lanes) {
> > case 1:
> > + plc |= PORT_LINK_MODE_1_LANES;
> > lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES;
> > break;
> > case 2:
> > + plc |= PORT_LINK_MODE_2_LANES;
> > lwsc |= PORT_LOGIC_LINK_WIDTH_2_LANES;
> > break;
> > case 4:
> > + plc |= PORT_LINK_MODE_4_LANES;
> > lwsc |= PORT_LOGIC_LINK_WIDTH_4_LANES;
> > break;
> > case 8:
> > + plc |= PORT_LINK_MODE_8_LANES;
> > lwsc |= PORT_LOGIC_LINK_WIDTH_8_LANES;
> > break;
> > + default:
> > + dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);
> > + return;
> > }
> > + dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
> > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
> > }
> >
> > @@ -1027,31 +1039,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
> > val |= PORT_LINK_DLL_LINK_EN;
> > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
> >
> > - if (!pci->num_lanes) {
> > - dev_dbg(pci->dev, "Using h/w default number of lanes\n");
> > - return;
> > - }
> > -
> > - /* Set the number of lanes */
> > - val &= ~PORT_LINK_MODE_MASK;
> > - switch (pci->num_lanes) {
> > - case 1:
> > - val |= PORT_LINK_MODE_1_LANES;
> > - break;
> > - case 2:
> > - val |= PORT_LINK_MODE_2_LANES;
> > - break;
> > - case 4:
> > - val |= PORT_LINK_MODE_4_LANES;
> > - break;
> > - case 8:
> > - val |= PORT_LINK_MODE_8_LANES;
> > - break;
> > - default:
> > - dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes);
> > - return;
> > - }
> > - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
> > -
> > dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
> > }
> > --
> > 2.25.1
> >
