Hi Bjorn, Regards, Thippeswamy H > -----Original Message----- > From: Bjorn Helgaas <helgaas@xxxxxxxxxx> > Sent: Saturday, May 13, 2023 1:03 AM > To: Havalige, Thippeswamy <thippeswamy.havalige@xxxxxxx> > Cc: linux-pci@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; > devicetree@xxxxxxxxxxxxxxx; krzysztof.kozlowski@xxxxxxxxxx; > bhelgaas@xxxxxxxxxx; michals@xxxxxxxxxx; robh+dt@xxxxxxxxxx; > Yeleswarapu, Nagaradhesh <nagaradhesh.yeleswarapu@xxxxxxx>; Gogada, > Bharat Kumar <bharat.kumar.gogada@xxxxxxx>; > lorenzo.pieralisi@xxxxxxx > Subject: Re: [PATCH v2 3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver > > On Fri, May 12, 2023 at 11:57:25AM +0530, Thippeswamy Havalige wrote: > > Add support for Xilinx XDMA Soft IP core as Root Port. > > ... > > > +#include <linux/of_pci.h> > > +#include <linux/irqchip/chained_irq.h> > > The trend seems to be to alphabetize the system includes above. - Agreed, fix it in next patch > > +#include "pcie-xilinx-common.h" > > + > > +#include "../pci.h" - Agreed, fix it in next patch > Put the pcie-xilinx-common.h include here, as you did for > pcie-xilinx-cpm.c: > > #include <linux/irqchip/chained_irq.h> > > #include "../pci.h" > #include "pcie-xilinx-common.h" - Agreed, fix it in next patch > pcie-xilinx.c has a very similar list of register definitions, which makes me > wonder why it can't share pcie-xilinx-common.h as well. > > Obviously it would take a bit of rework since it uses BIT(x) instead of just "x". > But you hide the "BIT()" inside IMR(), which is arguably slightly obscure since > the #define value is not a register mask: > > > +#define IMR(x) BIT(XILINX_PCIE_INTR_ ##x) > > I don't really care either way, but it seems like a possibly needless difference. > Bjorn
