On Mon, May 15, 2023 at 12:20:42PM -0700, Smita Koralahalli wrote: > On 5/11/2023 8:23 AM, Lukas Wunner wrote: > > Subject: [PATCH] PCI: pciehp: Disable Surprise Down Error reporting > > > > On hotplug ports capable of surprise removal, Surprise Down Errors are > > expected and no reason for AER or DPC to spring into action. Although > > a Surprise Down event might be caused by an error, software cannot > > discern that from regular surprise removal. > > > > Any well-behaved BIOS should mask such errors, but Smita reports a case > > where hot-removing an Intel NVMe SSD [8086:0a54] from an AMD Root Port > > [1022:14ab] results in irritating AER log messages and a delay of more > > than 1 second caused by DPC handling: [...] > Thanks for the patch. I tested it and I notice that the AER status registers > will still be set. I just don't see a DPC event with these settings. > > I have logged in the status registers after the device is removed in > pciehp_handle_presence_or_link_change(). [...] > Section 6.2.3.2.2 in PCIe Spec v6.0 has also mentioned that: > "If an individual error is masked when it is detected, its error status bit > is still affected, but no error reporting Message is sent to the Root > Complex, and the error is not recorded in the Header Log, TLP Prefix Log, or > First Error Pointer".. Thanks for the thorough testing. So the error is logged and next time a reporting message for a different error is sent to the Root Complex, that earlier Surprise Down Error will be seen and you'd get belated log messages for it, is that what you're saying? I guess I could amend the patch to let pciehp unconditionally clear the Surprise Down Error Status bit upon a DLLSC event. Does the patch otherwise do what you want, i.e. no irritating messages and no extra delay incurred by AER/DPC handling? Thanks! Lukas
