On Sun, Apr 02, 2023 at 03:13:47PM +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx>
>
> De-assert PERST in separate step after reset signals to fully comply
> the PCIe CEM clause 2.2.
I guess this refers to PCIe CEM r5.0, sec 2.2.
> This fixes some NVME detection issues on mt7986.
>
> Fixes: d3bf75b579b9 ("PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192")
> Signed-off-by: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx>
> ---
> Patch is taken from user Ruslan aka RRKh61 (permitted me to send it
> with me as author).
>
> https://forum.banana-pi.org/t/bpi-r3-nvme-connection-issue/14563/17
> ---
> drivers/pci/controller/pcie-mediatek-gen3.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> index b8612ce5f4d0..176b1a04565d 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> @@ -350,7 +350,13 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
> msleep(100);
>
> /* De-assert reset signals */
> - val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
> + val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
> + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
> +
> + msleep(100);
There should be a #define for the 100ms value since it is required by
the generic PCIe CEM spec, not by anything specific to mediatek. If
one already exists, we should use it. If not, we should add one.
pcie-tegra194.c and pcie-mediatek.c (at least) also have similar
delays and should also use the same #define. There are several other
drivers that contain "msleep(100)", but I didn't look to see their
purpose.
> + /* De-assert PERST# signals */
> + val &= ~(PCIE_PE_RSTB);
> writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
>
> /* Check if the link is up or not */
> --
> 2.34.1
>
>
