Hi Manivannan,
> From: Manivannan Sadhasivam, Sent: Saturday, April 22, 2023 10:49 PM
>
> On Tue, Apr 18, 2023 at 09:23:53PM +0900, Yoshihiro Shimoda wrote:
> > Add dw_pcie_link_set_max_cap_width() to set PCI_EXP_LNKCAP_MLW.
> > In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
> > the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
> > field there is another one which needs to be update. It's
>
> s/update/updated
Oops. I'll fix it.
> > LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
> > the very least the maximum link-width capability CSR won't expose
> > the actual maximum capability.
> >
> > [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > Version 4.60a, March 2015, p.1032
> > [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > Version 4.70a, March 2016, p.1065
> > [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > Version 4.90a, March 2016, p.1057
> > ...
> > [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
> > Version 5.40a, March 2019, p.1396
> > [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > Version 5.40a, March 2019, p.1266
> >
> > The commit description is suggested by Serge Semin.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> > ---
> > drivers/pci/controller/dwc/pcie-designware.c | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index c76fa78c6468..2413cd39310c 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -737,6 +737,21 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> > dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed);
> > }
> >
> > +void dw_pcie_link_set_max_cap_width(struct dw_pcie *pci, int num_lanes)
>
> static? Or if you want other drivers to make use of it, then define it as a
> common PCI function (not dwc specific) and also update one potential user
> (pci-mvebu.c). I think you need to do the later.
Oops. This should be static. But, this function cannot be for other uesrs because
this function needs to use dw_pcie_{read,write}l which are for dwc controllers.
Best regards,
Yoshihiro Shimoda
> - Mani
>
> > +{
> > + u32 val;
> > + u8 cap;
> > +
> > + if (!num_lanes)
> > + return;
> > +
> > + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > + val = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
> > + val &= ~PCI_EXP_LNKCAP_MLW;
> > + val |= num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT;
> > + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, val);
> > +}
> > +
> > static void dw_pcie_link_set_max_width(struct dw_pcie *pci, u32 num_lanes)
> > {
> > u32 val;
> > @@ -1073,6 +1088,7 @@ void dw_pcie_setup(struct dw_pcie *pci)
> > dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
> > }
> >
> > + dw_pcie_link_set_max_cap_width(pci, pci->num_lanes);
> > dw_pcie_link_set_max_width(pci, pci->num_lanes);
> > dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
> > }
> > --
> > 2.25.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
