On Tue, Apr 18, 2023 at 09:23:54PM +0900, Yoshihiro Shimoda wrote: > One of PCIe controllers have an unexpected register value on Which PCI controller? > the dbi+0x97b register. So, add a new capability flag "EDMA_UNROLL" > which would force the unrolled eDMA mapping for the problematic > device, as suggested by Serge Semin. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx> Should this patch have a Suggested-by tag? > --- > drivers/pci/controller/dwc/pcie-designware.c | 8 +++++++- > drivers/pci/controller/dwc/pcie-designware.h | 5 +++-- > 2 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 2413cd39310c..feb6ab9d4944 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -920,8 +920,14 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci) > * Indirect eDMA CSRs access has been completely removed since v5.40a > * thus no space is now reserved for the eDMA channels viewport and > * former DMA CTRL register is no longer fixed to FFs. > + * > + * Note some devices for unknown reason may have zeros in the eDMA CTRL Again, it is good to mention what controllers are exhibiting this behavior. - Mani > + * register even though the HW-manual explicitly states there must FFs > + * if the unrolled mapping is enabled. For such cases the low-level > + * drivers are supposed to manually activate the unrolled mapping to > + * bypass the auto-detection procedure. > */ > - if (dw_pcie_ver_is_ge(pci, 540A)) > + if (dw_pcie_ver_is_ge(pci, 540A) || dw_pcie_cap_is(pci, EDMA_UNROLL)) > val = 0xFFFFFFFF; > else > val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 8c08159ea08e..c4bdfed7b2e2 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -54,8 +54,9 @@ > > /* DWC PCIe controller capabilities */ > #define DW_PCIE_CAP_REQ_RES 0 > -#define DW_PCIE_CAP_IATU_UNROLL 1 > -#define DW_PCIE_CAP_CDM_CHECK 2 > +#define DW_PCIE_CAP_EDMA_UNROLL 1 > +#define DW_PCIE_CAP_IATU_UNROLL 2 > +#define DW_PCIE_CAP_CDM_CHECK 3 > > #define dw_pcie_cap_is(_pci, _cap) \ > test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) > -- > 2.25.1 > -- மணிவண்ணன் சதாசிவம்
