On 4/17/23 18:26, Rick Wertenbroek wrote:
> The RK3399 PCI endpoint core has 33 windows for PCIe space, now in the
> driver up to 32 fixed size (1M) windows are used and pages are allocated
> and mapped accordingly. The driver first used a single window and allocated
> space inside which caused translation issues (between CPU space and PCI
> space) because a window can only have a single translation at a given
> time, which if multiple pages are allocated inside will cause conflicts.
> Now each window is a single region of 1M which will always guarantee that
> the translation is not in conflict.
>
> Set the translation register addresses for physical function. As documented
> in the technical reference manual (TRM) section 17.5.5 "PCIe Address
> Translation" and section 17.6.8 "Address Translation Registers Description"
>
> Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Rick Wertenbroek <rick.wertenbroek@xxxxxxxxx>
> Tested-by: Damien Le Moal <dlemoal@xxxxxxxxxx>
[...]
> @@ -600,7 +582,8 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev)
>
> ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR;
>
> - rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE, PCIE_CLIENT_CONFIG);
> + rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE,
> + PCIE_CLIENT_CONFIG);
This change belongs to patch 3 of the series, not here.
Other than this, looks good. With that fixed,
Reviewed-by: Damien Le Moal <dlemoal@xxxxxxxxxx>
