Since this patch has nothing to do with ACPI, update subject line to: PCI: Add PCIe to PCI/PCI-X Bridge AER fields On Tue, Nov 15, 2022 at 11:12:44AM +0800, LeoLiu-oc wrote: > From: leoliu-oc <leoliu-oc@xxxxxxxxxxx> > > Define secondary uncorrectable error mask register, secondary > uncorrectable error severity register and secondary error capabilities and > control register bits in AER capability for PCIe to PCI/PCI-X Bridge. > Please refer to PCIe to PCI/PCI-X Bridge Specification, sec 5.2.3.2, > 5.2.3.3 and 5.2.3.4. Capitalize register names to match the spec usage. > Signed-off-by: leoliu-oc <leoliu-oc@xxxxxxxxxxx> Assuming this goes along with a patch series that adds uses of these definitions: Acked-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx> > --- > include/uapi/linux/pci_regs.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index 57b8e2ffb1dd..37f3baa336d7 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -799,6 +799,11 @@ > #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ > #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */ > > +/* PCIe advanced error reporting extended capabilities for PCIe to PCI/PCI-X Bridge */ > +#define PCI_ERR_UNCOR_MASK2 0x30 /* Secondary Uncorrectable Error Mask */ > +#define PCI_ERR_UNCOR_SEVER2 0x34 /* Secondary Uncorrectable Error Severit */ > +#define PCI_ERR_CAP2 0x38 /* Secondary Advanced Error Capabilities */ Please squash these right up next to the other PCI_ERR_* definitions so it's obvious that they overlap PCI_ERR_ROOT_STATUS and PCI_ERR_ROOT_ERR_SRC (which is fine since one device can't have both), e.g., #define PCI_ERR_ROOT_STATUS 0x30 #define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ ... #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */ #define PCI_ERR_UNCOR_MASK2 0x30 /* PCIe to PCI/PCI-X bridge */ #define PCI_ERR_UNCOR_SEVER2 0x34 /* PCIe to PCI/PCI-X bridge */ #define PCI_ERR_CAP2 0x38 /* PCIe to PCI/PCI-X bridge */ > /* Virtual Channel */ > #define PCI_VC_PORT_CAP1 0x04 > #define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ > -- > 2.20.1 >
