On 04/06/2023, 'Ajay Agarwal' via kernel-team wrote:
> Here is my attempt at a patch which can satisfy all the requirements
> (Ideally, I did not want to use `pci->ops` in the host driver but I
> could not figure out any other way):
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c
> b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 9952057c8819..39c7219ec7c9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -485,15 +485,18 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
> if (ret)
> goto err_remove_edma;
>
> - if (!dw_pcie_link_up(pci)) {
> - ret = dw_pcie_start_link(pci);
> + ret = dw_pcie_start_link(pci);
> + if (ret)
> + goto err_remove_edma;
> +
> + if (dw_pcie_link_up(pci)) {
> + dw_pcie_print_link_status(pci);
> + } else if (pci->ops && pci->ops->start_link) {
> + ret = dw_pcie_wait_for_link(pci);
> if (ret)
> - goto err_remove_edma;
> + goto err_stop_link;
> }
>
> - /* Ignore errors, the link may come up later */
> - dw_pcie_wait_for_link(pci);
> -
> bridge->sysdata = pp;
>
> ret = pci_host_probe(bridge);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 53a16b8b6ac2..03748a8dffd3 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -644,9 +644,20 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index)
> dw_pcie_writel_atu(pci, dir, index, PCIE_ATU_REGION_CTRL2, 0);
> }
>
> -int dw_pcie_wait_for_link(struct dw_pcie *pci)
> +void dw_pcie_print_link_status(struct dw_pcie *pci)
> {
> u32 offset, val;
> +
> + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> + val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
> +
> + dev_info(pci->dev, "PCIe Gen.%u x%u link up\n",
> + FIELD_GET(PCI_EXP_LNKSTA_CLS, val),
> + FIELD_GET(PCI_EXP_LNKSTA_NLW, val));
> +}
> +
> +int dw_pcie_wait_for_link(struct dw_pcie *pci)
> +{
> int retries;
>
> /* Check if the link is up or not */
> @@ -662,12 +673,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci)
> return -ETIMEDOUT;
> }
>
> - offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> - val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
> -
> - dev_info(pci->dev, "PCIe Gen.%u x%u link up\n",
> - FIELD_GET(PCI_EXP_LNKSTA_CLS, val),
> - FIELD_GET(PCI_EXP_LNKSTA_NLW, val));
> + dw_pcie_print_link_status(pci);
>
> return 0;
> }
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 79713ce075cc..615660640801 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -429,6 +429,7 @@ void dw_pcie_setup(struct dw_pcie *pci);
> void dw_pcie_iatu_detect(struct dw_pcie *pci);
> int dw_pcie_edma_detect(struct dw_pcie *pci);
> void dw_pcie_edma_remove(struct dw_pcie *pci);
> +void dw_pcie_print_link_status(struct dw_pcie *pci);
>
> static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
> {
>
> --
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>
Thanks Ajay for the follow-up patch! I've tested it out on a Pixel 6 and
it's working as intended for me. Probing the PCIe RC device now only
take 0.02s vs ~1.02s. If others don't object, please send it as a v3
patch.
Thanks,
Will
