On Wed, Mar 29, 2023 at 10:58:59PM +0530, Basavaraj Natikar wrote: > The AMD [1022:15b8] USB controller loses some internal functional > MSI-X context when transitioning from D0 to D3hot. BIOS normally > traps D0->D3hot and D3hot->D0 transitions so it can save and restore > that internal context, > but some firmware in the field lacks due to > AMD_15B8_RCC_DEV2_EPF0_STRAP2 NO_SOFT_RESET bit is set. This part doesn't have quite enough words in it. Does the following sound right? ... but some firmware in the field can't do this because it fails to clear the AMD_15B8_RCC_DEV2_EPF0_STRAP2 NO_SOFT_RESET bit. If not, let me know and I can update it. > Hence add quirk to clear AMD_15B8_RCC_DEV2_EPF0_STRAP2 NO_SOFT_RESET > bit before USB controller initialization during boot. > > Reported-by: Thomas Glanzmann <thomas@xxxxxxxxxxxx> > Link: https://lore.kernel.org/linux-usb/Y%2Fz9GdHjPyF2rNG3@xxxxxxxxxxxx/T/#u > Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@xxxxxxx> > Reviewed-by: Mario Limonciello <mario.limonciello@xxxxxxx> Applied to for-linus for v6.3, thank you for all your work on this! I updated the subject to: x86/PCI: Add quirk for AMD XHCI controller that loses MSI-X state in D3hot so it has a little bit of context. I also added a stable tag since I assume the same problem will occur on older kernels. Let me know if that's not appropriate. Bjorn > --- > arch/x86/pci/fixup.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c > index 615a76d70019..bf5161dcf89e 100644 > --- a/arch/x86/pci/fixup.c > +++ b/arch/x86/pci/fixup.c > @@ -7,6 +7,7 @@ > #include <linux/dmi.h> > #include <linux/pci.h> > #include <linux/vgaarb.h> > +#include <asm/amd_nb.h> > #include <asm/hpet.h> > #include <asm/pci_x86.h> > > @@ -824,3 +825,23 @@ static void rs690_fix_64bit_dma(struct pci_dev *pdev) > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7910, rs690_fix_64bit_dma); > > #endif > + > +#ifdef CONFIG_AMD_NB > + > +#define AMD_15B8_RCC_DEV2_EPF0_STRAP2 0x10136008 > +#define AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK 0x00000080L > + > +static void quirk_clear_strap_no_soft_reset_dev2_f0(struct pci_dev *dev) > +{ > + u32 data; > + > + if (!amd_smn_read(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, &data)) { > + data &= ~AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK; > + if (amd_smn_write(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, data)) > + pci_err(dev, "Failed to write data 0x%x\n", data); > + } else { > + pci_err(dev, "Failed to read data\n"); > + } > +} > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b8, quirk_clear_strap_no_soft_reset_dev2_f0); > +#endif > -- > 2.25.1 >
