On 06/04/2023 13:11, Minda Chen wrote:
> The PCIe is a PCIe2, single lane PCIe compliant controller.
>
> Signed-off-by: Minda Chen <minda.chen@xxxxxxxxxxxxxxxx>
> ---
> .../jh7110-starfive-visionfive-2.dtsi | 58 ++++++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 88 +++++++++++++++++++
> 2 files changed, 146 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index cf0a66faf5d3..4552919e69b0 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -191,6 +191,50 @@
> };
> };
>
> + pcie0_wake_default: pcie0_wake_default {
No underscores in node names. Test your patches against bindings before
sending.
> uart0_pins: uart0-0 {
> tx-pins {
> pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
> @@ -228,3 +272,17 @@
> dr_mode = "peripheral";
> status = "okay";
> };
> +
> +&pcie0 {
> + pinctrl-names = "default";
> + reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
> + phys = <&pciephy0>;
> + status = "okay";
> +};
> +
> +&pcie1 {
> + pinctrl-names = "default";
> + reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
> + phys = <&pciephy1>;
> + status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 2f67196ffac0..c309ec550ba7 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -642,5 +642,93 @@
> #reset-cells = <1>;
> power-domains = <&pwrc JH7110_PD_VOUT>;
> };
> +
> + pcie0: pcie@2B000000 {
Lower case hex.
> + compatible = "starfive,jh7110-pcie";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
Why reg is not second property?
> + reg = <0x0 0x2B000000 0x0 0x1000000
> + 0x9 0x40000000 0x0 0x10000000>;
> + reg-names = "reg", "config";
> + device_type = "pci";
> + starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
> + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
> + interrupts = <56>;
Your binding requires cells, so I am pretty sure you did not test what
you wrote.
Best regards,
Krzysztof
