On 16/03/23 12:41, Achal Verma wrote:
> From: Jasko-EXT Wojciech <wojciech.jasko-EXT@xxxxxxxxxxxxxxxxxxxxxxxxxxx>
>
> Next Function Number field in ARI Capability Register for last function
> must be zero by default as per the PCIe specification, indicating there
> is no next higher number function but that's not happening in our case,
> so this patch clears the Next Function Number field for last function used.
>
> Signed-off-by: Jasko-EXT Wojciech <wojciech.jasko-EXT@xxxxxxxxxxxxxxxxxxxxxxxxxxx>
> Signed-off-by: Achal Verma <a-verma1@xxxxxx>
> ---
> Changes from v1:
> * Fix commments in the code.
>
> Changes from v2:
> * Rework the commit message.
>
> drivers/pci/controller/cadence/pcie-cadence-ep.c | 14 +++++++++++++-
> drivers/pci/controller/cadence/pcie-cadence.h | 6 ++++++
> 2 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> index b8b655d4047e..8742b2f594fd 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> @@ -565,7 +565,8 @@ static int cdns_pcie_ep_start(struct pci_epc *epc)
> struct cdns_pcie *pcie = &ep->pcie;
> struct device *dev = pcie->dev;
> int max_epfs = sizeof(epc->function_num_map) * 8;
> - int ret, value, epf;
> + int ret, epf, last_fn;
> + u32 reg, value;
>
> /*
> * BIT(0) is hardwired to 1, hence function 0 is always enabled
> @@ -573,6 +574,17 @@ static int cdns_pcie_ep_start(struct pci_epc *epc)
> */
> cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, epc->function_num_map);
>
> + /*
> + * Next function field in ARI_CAP_AND_CTR register for last function
> + * should be 0.
> + * Clearing Next Function Number field for the last function used.
> + */
> + last_fn = find_last_bit(&epc->function_num_map, BITS_PER_LONG);
> + reg = CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(last_fn);
> + value = cdns_pcie_readl(pcie, reg);
> + value &= ~CDNS_PCIE_ARI_CAP_NFN_MASK;
> + cdns_pcie_writel(pcie, reg, value);
> +
> if (ep->quirk_disable_flr) {
> for (epf = 0; epf < max_epfs; epf++) {
> if (!(epc->function_num_map & BIT(epf)))
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> index 190786e47df9..68c4c7878111 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> @@ -130,6 +130,12 @@
> #define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0
> #define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200
>
> +/*
> + * Endpoint PF Registers
> + */
> +#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000)
> +#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8)
> +
> /*
> * Root Port Registers (PCI configuration space for the root port function)
> */
Reviewed-by: Vignesh Raghavendra <vigneshr@xxxxxx>
FYI, there seems to be a duplicate patch [1], you may want to clarify
which one to look at
[1] https://lore.kernel.org/all/20230316065455.191785-1-a-verma1@xxxxxx/
--
Regards
Vignesh
