[+cc Serge, who has done most of the recent work in this file]
On Mon, Mar 13, 2023 at 02:40:16PM +0200, Elad Nachman wrote:
> From: Elad Nachman <enachman@xxxxxxxxxxx>
>
> Allow dts override of region limit for SOCs with older Synopsis
> Designware PCIe IP but with greater than 32-bit address range support,
> such as the Armada 7020/7040/8040 family of SOCs by Marvell,
> when the DT file places the PCIe window above the 4GB region.
> The Synopsis Designware PCIe IP in these SOCs is too old to specify the
> highest memory location supported by the PCIe, but practically supports
> such locations. Allow these locations to be specified in the DT file.
> DT property is called num-regionmask , and can range between 33 and 64.
s/Synopsis/Synopsys/ (several occurrences)
s/Designware/DesignWare/ (several occurrences)
Remove space before comma.
> Signed-off-by: Elad Nachman <enachman@xxxxxxxxxxx>
> ---
> v4:
> 1) Fix blank lines removal / addition
>
> 2) Remove usage of variable with same name as dt binding property
>
> drivers/pci/controller/dwc/pcie-designware.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 53a16b8b6ac2..9773c110c733 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -735,8 +735,10 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> void dw_pcie_iatu_detect(struct dw_pcie *pci)
> {
> int max_region, ob, ib;
> - u32 val, min, dir;
> + u32 val, min, dir, ret;
> u64 max;
> + struct device *dev = pci->dev;
> + struct device_node *np = dev->of_node;
>
> val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
> if (val == 0xFFFFFFFF) {
> @@ -781,7 +783,13 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
> dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT, 0xFFFFFFFF);
> max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT);
> } else {
> - max = 0;
> + /* Allow dts override of region limit for older IP with above 32-bit support: */
Reflow comment to fit in 80 columns.
> + ret = of_property_read_u32(np, "num-regionmask", &val);
> + if (!ret && val > 32) {
> + max = GENMASK(val - 33, 0);
> + dev_info(pci->dev, "Overriding region limit to %u bits\n", val);
> + } else
> + max = 0;
> }
>
> pci->num_ob_windows = ob;
> --
> 2.17.1
>
