On Tue, 28 Feb 2023 at 14:20, Manivannan Sadhasivam <mani@xxxxxxxxxx> wrote: > > On Thu, Feb 02, 2023 at 10:42:15AM +0100, Arnd Bergmann wrote: > > On Thu, Feb 2, 2023, at 10:16, Robert Marko wrote: > > > On Mon, 30 Jan 2023 at 18:11, Arnd Bergmann <arnd@xxxxxxxx> wrote: > > >> On Fri, Jan 13, 2023, at 17:44, Robert Marko wrote: > > > > > > As pointed out in the commit description, the ranges property was copied > > > from the QCA-s downstream 5.4 kernel [1] as I dont have any documentation > > > on the SoC. > > > > > > I have runtime tested this on Xiaomi AX3600 which has a QCA9889 card on the > > > Gen3 PCIe port, and on Xiaomi AX9000 which has QCA9889 on Gen2 port > > > and QCN9074 on the Gen3 port and they are working fine. > > > > Neither of those use I/O ports though, nor does any other sensible > > device that was made in the past decade. > > > > The compatible string tells me that this is a designware pcie block, > > so I think driver actually sets up the mapping based on the ranges > > property in DT in dw_pcie_iatu_detect() and dw_pcie_iatu_setup(), > > rather than the mapping being determined by hardware or firmware > > in advance. > > > > Not sure about the general policy we have for this case, maybe the > > pci controller or pci-dwc maintainers have an idea here. I would > > think it's better to either have no I/O ranges in DT or have > > sensible ones than ones that are clearly bogus, if the controller > > is able to set up the ranges. > > > > Just happen to see this thread and I agree that the I/O port range is indeeed > bogus. This is due to the fact that no one tested I/O range with a compatible > device. > > I'm not sure about the PCI policy though but we should fix the mapping across > all SoCs. I will send out a series for that. Thanks for sorting this out. Regards, Robert > > Thanks for spotting, Arnd! > > - Mani > > > Arnd > > -- > மணிவண்ணன் சதாசிவம்
