On 2/17/2023 2:13 PM, Sricharan Ramabadhran wrote:
Hi Devi,
On 2/14/2023 10:11 PM, Devi Priya wrote:
Add the clocks needed for enabling PCIe in IPQ9574
Co-developed-by: Anusha Rao <quic_anusha@xxxxxxxxxxx>
Signed-off-by: Anusha Rao <quic_anusha@xxxxxxxxxxx>
Signed-off-by: Devi Priya <quic_devipriy@xxxxxxxxxxx>
---
drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c
b/drivers/clk/qcom/gcc-ipq9574.c
index b2a2d618a5ec..1bf33d582dc2 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -1538,6 +1538,24 @@ static struct clk_regmap_phy_mux
pcie0_pipe_clk_src = {
},
};
+static struct clk_branch gcc_pcie0_pipe_clk = {
+ .halt_reg = 0x28044,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x28044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie0_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
Also, this patch should come before your phy driver updates.
Sure got it, will reorder the patches in V2
Regards,
Sricharan
Best Regards,
Devi Priya
