On 2/16/23 17:43, Rick Wertenbroek wrote:
> On Thu, Feb 16, 2023 at 8:28 AM Damien Le Moal
> <damien.lemoal@xxxxxxxxxxxxxxxxxx> wrote:
>>
>> On 2/15/23 18:58, Damien Le Moal wrote:
>> [...]
>>> WRITE ( 131072 bytes): OKAY
>>> WRITE (1024000 bytes): OKAY
>>>
>>> Then stops here doing the 1024001 B case. The host waits for a completion that
>>> does not come. On the EP side, I see:
>>>
>>> [ 94.307215] pci_epf_test pci_epf_test.0: READ src addr 0xffd00000, 1024001 B
>>> [ 94.307960] pci_epc fd000000.pcie-ep: Map region 1 phys addr 0xfa100000 to
>>> pci addr 0xffd00000, 1024001 B
>>> [ 94.308924] rockchip-pcie-ep fd000000.pcie-ep: Set atu: region 1, cpu addr
>>> 0xfa100000, pci addr 0xffd00000, 1024001 B
>>> [ 132.309645] dma-pl330 ff6e0000.dma-controller: Reset Channel-2
>>> CS-20000e FTC-40000
>>>
>>> ^^^^^^^^^^^^^^^
>>> The DMA engine does not like something at all. Back to where I was when I tried
>>> your series initially, which is why I tried removing patch 1 to see what happens...
>>>
>>> [ 132.370479] pci_epf_test pci_epf_test.0: READ => Size: 1024001 B, DMA: YES,
>>> Time: 38.059623935 s, Rate: 26 KB/s
>>> [ 132.372152] pci_epc fd000000.pcie-ep: Unmap region 1
>>> [ 132.372780] pci_epf_test pci_epf_test.0: RAISE MSI IRQ 1
>>> [ 132.373312] rockchip-pcie-ep fd000000.pcie-ep: Send MSI IRQ 1
>>> [ 132.373844] rockchip-pcie-ep fd000000.pcie-ep: MSI disabled
>>> [ 132.374388] pci_epf_test pci_epf_test.0: Raise IRQ failed -22
>>>
>>> And it looks like the PCI core crashed or something because MSI does not work
>>> anymore as well (note that this is wheat I see with my nvme epf driver too, but
>>> I do not have that DMA channel reset message...)
>>>
>>> If I run the tests without DMA (mmio only), everything seems fine:
>>>
>>> ## Read Tests (No DMA)
>>> READ ( 1 bytes): OKAY
>>> READ ( 1024 bytes): OKAY
>>> READ ( 1025 bytes): OKAY
>>> READ (1024000 bytes): OKAY
>>> READ (1024001 bytes): OKAY
>>>
>>> ## Write Tests (No DMA)
>>> WRITE ( 1 bytes): OKAY
>>> WRITE ( 1024 bytes): OKAY
>>> WRITE ( 1025 bytes): OKAY
>>> WRITE (1024000 bytes): OKAY
>>> WRITE (1024001 bytes): OKAY
>>>
>>> ## Copy Tests (No DMA)
>>> COPY ( 1 bytes): OKAY
>>> COPY ( 1024 bytes): OKAY
>>> COPY ( 1025 bytes): OKAY
>>> COPY (1024000 bytes): OKAY
>>> COPY (1024001 bytes): OKAY
>>>
>>> So it looks like translation is working with your patch, but that the driver is
>>> still missing something for DMA to work correctly...
>>
>> I kept testing this and realized that I was not getting a consistent behavior.
>> Sometimes all tests passed, but would not repeat (running again would fail
>> everything), sometimes NMIs from bad accesses, and other times "hang" (test not
>> completing but no real machine hang/crash). So it started to hint at something
>> randomly initialized...
>>
>> Re-reading the TRM, particularly section 17.5.5.1.1, I realized that the lower
>> 16 bits of the desc2 register are used for the translation, but we never set
>> them with the current code. Only desc0 and desc1... So I added a write(0) to
>> desc2 and now it is finally working well. Running the tests in a loop, they all
>> pass and no bad behavior is observed.
>>
>> My cleaned-up rockchip_pcie_prog_ep_ob_atu() function now looks like this:
>>
>> static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn,
>> u32 r, u32 type, u64 phys_addr,
>> u64 pci_addr, size_t size)
>> {
>> u64 sz = 1ULL << fls64(size - 1);
>> int num_pass_bits = ilog2(sz);
>> u32 addr0, addr1, desc0;
>>
>> /* Sanity checks */
>> if (WARN_ON_ONCE(type == AXI_WRAPPER_NOR_MSG))
>> return;
>> if (WARN_ON_ONCE(ALIGN_DOWN(phys_addr, SZ_1M) != phys_addr))
>> return;
>> if (WARN_ON_ONCE(rockchip_ob_region(phys_addr + size - 1) != r))
>> return;
>>
>> /* We must pass at least 8 bits of PCI bus address */
>> if (num_pass_bits < 8)
>> num_pass_bits = 8;
>>
>> /* PCI bus address region */
>> addr0 = ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |
>> (lower_32_bits(pci_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
>> addr1 = upper_32_bits(pci_addr);
>> desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(fn) | type;
>>
>> rockchip_pcie_write(rockchip, addr0,
>> ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r));
>> rockchip_pcie_write(rockchip, addr1,
>> ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r));
>> rockchip_pcie_write(rockchip, desc0,
>> ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r));
>> rockchip_pcie_write(rockchip, 0,
>> ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r));
>> rockchip_pcie_write(rockchip, 0,
>> ROCKCHIP_PCIE_AT_OB_REGION_DESC2(r));
>> }
>>
>> And the function rockchip_pcie_clear_ep_ob_atu() also clears desc2:
>>
>> static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip,
>> u32 region)
>> {
>> rockchip_pcie_write(rockchip, 0,
>> ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(region));
>> rockchip_pcie_write(rockchip, 0,
>> ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(region));
>> rockchip_pcie_write(rockchip, 0,
>> ROCKCHIP_PCIE_AT_OB_REGION_DESC0(region));
>> rockchip_pcie_write(rockchip, 0,
>> ROCKCHIP_PCIE_AT_OB_REGION_DESC1(region));
>> rockchip_pcie_write(rockchip, 0,
>> ROCKCHIP_PCIE_AT_OB_REGION_DESC2(region));
>> }
>>
>> Thoughts ?
>>
>> --
>> Damien Le Moal
>> Western Digital Research
>>
>
> desc2 dictates the bits [79-64] of the PCIe header descriptor.
> These bits are for the PF TLP Processing hints.
> I did not set them because I thought the default value (0) would be fine.
> The TRM section 17.6.8.2.5 says that this register values are reset
> to 0, therefore, the write here (0) to desc2 should not change anything unless
> that register is written somewhere (I don't think it is).
> Anyways, it's not a bad idea to set desc2 to 0 in those two functions.
I wonder if that register changes when TLPs are processed... So when the region
is remapped, previous values still there cause the problems I am seeing ?
As mentioned, with this "fix", the pcitest.sh is now solid. But I am still
seeing the same issues with my nvme endpoint driver when Linux takes over from
BIOS. Bios works, but not Linux, still no IRQs at all. So there is likely still
another issue that I cannot see at the moment. No hints whatsoever.
--
Damien Le Moal
Western Digital Research
