Hi Serge,
> From: Serge Semin, Sent: Monday, February 13, 2023 6:11 AM
>
> On Fri, Feb 10, 2023 at 10:49:11PM +0900, Yoshihiro Shimoda wrote:
> > Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0)
> > PCIe endpoint module.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
> > ---
> > .../bindings/pci/rcar-gen4-pci-ep.yaml | 90 +++++++++++++++++++
> > 1 file changed, 90 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
> b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
> > new file mode 100644
> > index 000000000000..4b10d67e4336
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
> > @@ -0,0 +1,90 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (C) 2022 Renesas Electronics Corp.
> > +%YAML 1.2
> > +---
> > +$id:
<snip URL>
> > +$schema:
<snip URL>
> > +
> > +title: Renesas R-Car Gen4 PCIe Endpoint
> > +
> > +maintainers:
> > + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> > +
> > +allOf:
> > + - $ref: snps,dw-pcie-ep.yaml#
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: renesas,r8a779f0-pcie-ep # R-Car S4-8
> > + - const: renesas,rcar-gen4-pcie-ep # R-Car Gen4
> > +
> > + reg:
> > + maxItems: 4
> > +
> > + reg-names:
> > + items:
> > + - const: dbi
> > + - const: atu
>
> > + - const: appl
>
> Please, use "elbi" or "app" instead. No need in using the
> vendor-specific names if there is the generic ones.
> (* @Rob, that's why I was insisting in failing the DT-bindings
> evaluation for such cases...)
> See Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml:98
I got it. I'll fix it.
> > + - const: addr_space
> > +
> > + interrupts:
> > + maxItems: 3
> > +
> > + interrupt-names:
> > + items:
>
> > + - const: dma
>
> Are you sure there is a single IRQ line for all eDMA channels?
Yes.
> Judging by the DW PCIe HW manual the eDMA events are signaled by the
> wires: edma_int[((CC_NUM_DMA_RD_CHAN+CC_NUM_DMA_WR_CHAN)-1):0]. If you
> have a single signal then they must have been combined on the way to
> the GIC though...
I think so.
The drivers/dma/dw-edma/dw-edma-core.c seems to support nr_irqs == 1.
> > + - const: sft_ce
> > + - const: app
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
>
> > + max-link-speed: true
>
> This prop is determined by the CX_MAX_PCIE_SPEED IP-core synthesize
> parameter.
>
> > +
> > + num-lanes: true
>
> This is determined by the CX_NL IP-core synthesize parameter.
>
> Thus you can provide at least the 'maximum' constraint for
> the properties above.
I'll add 'maximum' to each property.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-names
> > + - interrupts
> > + - resets
> > + - power-domains
> > + - clocks
> > +
> > +additionalProperties: false
>
> Are you sure that none of the next properties will be ever used in
> the R-Car PCIe End-point DT-nodes?
> max-functions
> max-virtual-functions
> phys
> phy-names
> reset-gpios
> snps,enable-cdm-check
> dma-coherent
> * etc
>
> I am pretty much sure that the reset-gpios (platform-specific),
> max-{virtual-}functions (determined by the CX_NFUNC IP-core synthesize
> parameter), phys/phy-names (you had a PHYs CSR space in the
> DT-bindings example) and dma-coherent properties are relevant for your
> device. At the very least the 'max-functions' prop constraint could be
> explicitly added to your DT-bindings file. You must be aware of how
> many functions the R-Car PCIe EP support, right?
The R-Car PCIe EP supports two functions. So, I'll add 'max-functions'
property with 'maximum: 2'.
> The rest of the
> properties could be implicitly evaluated by replacing the
> "additionalProperties: false" flag with the "unevaluatedProperties:
> false" statement.
I got it. I'll change "additionalProperties: false" to
"unevaluatedProperties: false".
Best regards,
Yoshihiro Shimoda
> -Serge(y)
>
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/power/r8a779f0-sysc.h>
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + pcie0_ep: pcie-ep@e65d0000 {
> > + compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep";
> > + reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d1000 0 0x1000>,
> > + <0 0xe65d3000 0 0x2000>, <0 0xfe000000 0 0x400000>;
> > + reg-names = "dbi", "atu", "appl", "addr_space";
> > + interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "dma", "sft_ce", "app";
> > + clocks = <&cpg CPG_MOD 624>;
> > + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
> > + resets = <&cpg 624>;
> > + num-lanes = <2>;
> > + max-link-speed = <2>;
> > + };
> > + };
> > --
> > 2.25.1
> >
> >
