On 23-02-03 10:56:31, Johan Hovold wrote:
> On Fri, Feb 03, 2023 at 10:18:07AM +0200, Abel Vesa wrote:
> > Enable PCIe controllers and PHYs nodes on SM8550 MTP board.
> >
> > Co-developed-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> > Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
> > ---
>
> > +&pcie_1_phy_aux_clk {
> > + clock-frequency = <1000>;
> > +};
> > +
> > +&pcie0 {
> > + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
> > + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pcie0_default_state>;
> > +
> > + status = "okay";
> > +};
> > +
> > +&pcie0_phy {
> > + vdda-phy-supply = <&vreg_l1e_0p88>;
> > + vdda-pll-supply = <&vreg_l3e_1p2>;
>
> Super nit: add newline for consistency.
>
> > + status = "okay";
> > +};
> > +
> > +&pcie1 {
> > + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
> > + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
>
> Neither controller needs the new enable gpio?
Nope, none of the controllers need it.
>
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pcie1_default_state>;
> > +
> > + status = "okay";
> > +};
> > +
> > +&pcie1_phy {
> > + vdda-phy-supply = <&vreg_l3c_0p91>;
> > + vdda-pll-supply = <&vreg_l3e_1p2>;
> > + vdda-qref-supply = <&vreg_l1e_0p88>;
> > +
> > + status = "okay";
> > +};
> > +
> > &pm8550_gpios {
> > sdc2_card_det_n: sdc2-card-det-state {
> > pins = "gpio12";
>
> Johan
