On Thu, Jan 26, 2023 at 02:50:44PM +0100, Rick Wertenbroek wrote: > The Rockchip PCIe controller did not wait until the PHY PLLs were locked. > This could cause hangs. Now the PHY PLLs status is checked through a side > channel bit with a poll and timeout. If the PHY PLLs cannot lock an error > is generated. This is documented in the TRM section 17.5.8.1 PCIe > Initalization Sequence. s/Initalization/Initialization/
