On Wed, 2012-02-08 at 07:58 -0800, Bjorn Helgaas wrote: > The only architecture-specific thing here is discovering the range of > bus numbers below a host bridge. The architecture should not have to > mess around with pci_bus_update_busn_res_end() like this. It should > be able to say "here's my bus number range" (and of course the PCI > core can default to 0-255 if the arch doesn't supply a range) and the > core should take care of the rest. So it's a bit messy in here because we deal with several things. What the firmware gives us is the range it assigned, but that isn't necessarily the HW limits (almost never is in fact). In some cases we honor it, for example when in "probe only" mode where we prevent any reassigning, and in some case, we ignore it and let the PCI core renumber things (typically because the FW "forgot" to set aside bus numbers for a cardbus slot for example, that sort of things). So it's a bit of a tricky situation. Off the top of my head, I'm pretty sure that most if not all of our PCI host bridges simply support a full 0...255 range and there is no sharing between bridges like on x86, they are just different domains. But I can't vouch 100% for some of the oddball cases like Pegasos or some freescale gear. Cheers, Ben. -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
