[PATCH v2 0/3] PCI reset delay fixes

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Delay fixes for recovery from Secondary Bus Resets and Downstream Port
Containment, v2:


Changes v1 -> v2:

* [PATCH 1/3] PCI/PM: Observe reset delay irrespective of bridge_d3
  * Add Reviewed-by tags (Mika, Sathyanarayanan)

* [PATCH 2/3] PCI: Unify delay handling for reset and resume
  * Introduce PCI_RESET_WAIT macro for 1 sec timeout prescribed by
    PCIe r6.0 sec 6.6.1 (Bjorn)
  * Note in kernel-doc of pci_bridge_wait_for_secondary_bus()
    that timeout parameter is in milliseconds (Bjorn)
  * Add Reviewed-by tags (Mika, Sathyanarayanan)

* [PATCH 3/3] PCI/DPC: Await readiness of secondary bus after reset
  * Move PCIE_RESET_READY_POLL_MS macro below the newly introduced
    PCI_RESET_WAIT from patch [2/3] and extend its code comment
  * Mention errors seen on Ponte Vecchio in commit message (Bjorn)
  * Avoid first person plural in commit message (Sathyanarayanan)
  * Add Reviewed-by tag (Mika)


Link to v1:

https://lore.kernel.org/linux-pci/cover.1672511016.git.lukas@xxxxxxxxx/


Lukas Wunner (3):
  PCI/PM: Observe reset delay irrespective of bridge_d3
  PCI: Unify delay handling for reset and resume
  PCI/DPC: Await readiness of secondary bus after reset

 drivers/pci/pci-driver.c |  2 +-
 drivers/pci/pci.c        | 59 +++++++++++++++++-----------------------
 drivers/pci/pci.h        | 16 ++++++++++-
 drivers/pci/pcie/dpc.c   |  4 +--
 4 files changed, 43 insertions(+), 38 deletions(-)

-- 
2.39.0




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