On 2023-01-13 12:04, Lorenzo Pieralisi wrote:
On Thu, Dec 15, 2022 at 02:53:04AM +0300, Serge Semin wrote:
The DW PCIe RC IP-core is synthesized with the 64-bits AXI address bus.
Since the device is also equipped with the eDMA engine we need to
explicitly set the device DMA-mask so the DMA-engine clients would be able
to allocate the data buffers from the DMA-able memory space.
Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
---
Changelog v7:
- This is a new patch added on v7 stage of the series. (@Robin)
---
drivers/pci/controller/dwc/pcie-bt1.c | 4 ++++
1 file changed, 4 insertions(+)
Hi Robin,
are you OK with this change ? I think that's the last (PCI) bit we
need to take the series.
Yup, having gone and double-checked the context this seems fine too -
I've slightly lost track of all the circles we've been round in by now,
but it looks like the way things all end up after v8 (and now v9) should
be uncontentious.
Thanks,
Robin.
Thanks,
Lorenzo
diff --git a/drivers/pci/controller/dwc/pcie-bt1.c b/drivers/pci/controller/dwc/pcie-bt1.c
index 8b6c7d544d9a..04aa58348aa5 100644
--- a/drivers/pci/controller/dwc/pcie-bt1.c
+++ b/drivers/pci/controller/dwc/pcie-bt1.c
@@ -583,6 +583,10 @@ static int bt1_pcie_add_port(struct bt1_pcie *btpci)
struct device *dev = &btpci->pdev->dev;
int ret;
+ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
+ if (ret)
+ return ret;
+
btpci->dw.version = DW_PCIE_VER_460A;
btpci->dw.dev = dev;
btpci->dw.ops = &bt1_pcie_ops;
--
2.38.1
