Add the generic 'max-link-speed' property to describe the Gen2 PCIe link
generation limit.
This allows the generic DWC code to configure the link speed correctly.
Signed-off-by: Robert Marko <robimarko@xxxxxxxxx>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 06e1da176334..5ef4383ab18b 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -801,6 +801,7 @@ pcie1: pci@10000000 {
linux,pci-domain = <1>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
+ max-link-speed = <2>;
#address-cells = <3>;
#size-cells = <2>;
--
2.39.0
