On Fri, Oct 14, 2022 at 12:08:50AM +0530, Vidya Sagar wrote:
> Reduce the AXI slave timeout value to 7ms to be in line with the CBB
It would be good to understand where this 7ms delay comes from.
Please spell out what CBB is.
> logic's timeout value and to avoid CBB reporting errors because of no
> response from the PCIe IPs AXI slave logic for configuration space accesses
> through ECAM when the PCIe link is down. Also, set the Completion Timeout
> value to Range-A: 1ms~10ms to be inline with the AXI timeout value.
>
> Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx>
> ---
> V3:
> * This is a new patch in this series
>
> drivers/pci/controller/dwc/pcie-tegra194.c | 24 ++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 23ca97401339..7890e0c0c0d2 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -198,6 +198,12 @@
> #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFFFFFF 1
> #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 2
>
> +#define PORT_LOGIC_AMBA_LINK_TIMEOUT 0x8D4
> +#define AMBA_LINK_TIMEOUT_PERIOD_MASK GENMASK(7, 0)
> +#define AMBA_LINK_TIMEOUT_PERIOD_VAL 0x7
> +
> +#define PCI_EXP_DEVCTL2_CPL_TO_VAL 0x2 /* Range-A: 1ms to 10ms */
> +
> #define MSIX_ADDR_MATCH_LOW_OFF 0x940
> #define MSIX_ADDR_MATCH_LOW_OFF_EN BIT(0)
> #define MSIX_ADDR_MATCH_LOW_OFF_MASK GENMASK(31, 2)
> @@ -922,6 +928,18 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
> AMBA_ERROR_RESPONSE_CRS_SHIFT);
> dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val);
>
> + /* Reduce the AXI slave Timeout value to 7ms */
> + val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_LINK_TIMEOUT);
> + val &= ~AMBA_LINK_TIMEOUT_PERIOD_MASK;
> + val |= AMBA_LINK_TIMEOUT_PERIOD_VAL;
> + dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_LINK_TIMEOUT, val);
> +
> + /* Set the Completion Timeout value in 1ms~10ms range */
> + val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL2);
> + val_16 &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
> + val_16 |= PCI_EXP_DEVCTL2_CPL_TO_VAL;
> + dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL2, val_16);
> +
> /* Configure Max lane width from DT */
> val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
> val &= ~PCI_EXP_LNKCAP_MLW;
> @@ -1988,6 +2006,12 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
> val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
> dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
>
> + /* Set the Completion Timeout value in 1ms~10ms range */
> + val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL2);
> + val_16 &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
> + val_16 |= PCI_EXP_DEVCTL2_CPL_TO_VAL;
> + dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL2, val_16);
> +
> /* Clear Slot Clock Configuration bit if SRNS configuration */
> if (pcie->enable_srns) {
> val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
> --
> 2.17.1
>
>
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