Hi Lukas, On Sat, Dec 31, 2022 at 07:33:36PM +0100, Lukas Wunner wrote: > When recovering from a DPC reset, we neglect to observe the delays > prescribed by PCIe r6.0 sec 6.6.1 before accessing devices on the > secondary bus. As a result, devices which take a little longer to > recover remain inaccessible because their config space is restored > too early. > > One affected device is Intel's Ponte Vecchio HPC GPU. Ravi Kishore > kindly tested that this series solves the issue. > > > As a byproduct, the series fixes a similar delay issue for Secondary > Bus Resets. Sheng Bi proposed a patch last May, a variation of which > is contained herein: > > https://patchwork.kernel.org/project/linux-pci/patch/20220523171517.32407-1-windy.bi.enflame@xxxxxxxxx/ > > > A second byproduct of this series is an optimization for Secondary > Bus Resets whereby the delay after reset is reduced on modern PCIe > systems. Yang Su and Stanislav Spassov proposed a patch in August > which is subsumed by the present series: > > https://patchwork.kernel.org/project/linux-pci/patch/4315990a165dd019d970633713cf8e06e9b4c282.1660746147.git.yang.su@xxxxxxxxxxxxxxxxx/ > > > If the present series is accepted, the two above-linked patches > can be closed in patchwork. (For some reason, Sheng Bi's patch > is in "New" state, but marked "Archived".) > > Thanks! > > > Lukas Wunner (3): > PCI/PM: Observe reset delay irrespective of bridge_d3 > PCI: Unify delay handling for reset and resume > PCI/DPC: Await readiness of secondary bus after reset All look good to me, Reviewed-by: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx>
