On Thu, Nov 24, 2022 at 10:37:53AM +0100, Thomas Gleixner wrote:
> On Thu, Nov 24 2022 at 03:17, Kevin Tian wrote:
> >> static const struct msi_parent_ops dmar_msi_parent_ops = {
> >> - .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED |
> >> MSI_FLAG_MULTI_PCI_MSI,
> >> + .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED |
> >> + MSI_FLAG_MULTI_PCI_MSI |
> >> + MSI_FLAG_PCI_IMS,
> >> .prefix = "IR-",
> >> .init_dev_msi_info = msi_parent_init_dev_msi_info,
> >> };
> >
> > vIR is already available on vIOMMU today [1].
> >
> > Fortunately both intel/amd IOMMU has a way to detect whether it's a vIOMMU.
> >
> > For intel it's cap_caching_mode().
> >
> > For AMD it's amd_iommu_np_cache.
> >
> > Then MSI_FLAG_PCI_IMS should be set only on physical IOMMU.
>
> Ok. Let me fix that then.
>
> But that made me read back some more.
>
> Jason said, that the envisioned Mellanox use case does not depend on the
> IOMMU because the card itself has one which takes care of the
> protections.
Right, but that doesn't mean we need the physical iommu turned
off. Setting the mlx pci device to identity mode is usually enough to
get back to full performance.
> How are we going to resolve that dilemma?
The outcome is we don't have a strategy right now to make IMS work in
VMs. This series is all about making it work on physical machines,
that has to be a good first step.
I'm hoping the OCP work stream on SIOV will tackle how to fix the
interrupt problems. Some of the ideas I've seen could be formed into
something that would work in a VM.
Jason
