On Wed, Nov 16, 2022 at 01:54:57PM +0000, daire.mcnamara@xxxxxxxxxxxxx wrote: > From: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx> > > The SEC and DED interrupt bits were the wrong way round so the SEC > interrupt handler attempted to mask, unmask, and clear the DED interrupt > and vice versa. Correct the bit offsets so each interrupt handler > operates properly. Firstly, does this need a fixes tag for backporting? If it does, then you should probably put this as patch #1 in the series. > Signed-off-by: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx> > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > --- > drivers/pci/controller/pcie-microchip-host.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c > index 80e7554722ca..30153fd1a2b3 100644 > --- a/drivers/pci/controller/pcie-microchip-host.c > +++ b/drivers/pci/controller/pcie-microchip-host.c > @@ -165,12 +165,12 @@ > #define EVENT_PCIE_DLUP_EXIT 2 > #define EVENT_SEC_TX_RAM_SEC_ERR 3 > #define EVENT_SEC_RX_RAM_SEC_ERR 4 > -#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 5 > -#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 6 > +#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 5 > +#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 6 The order in the registers is: TX_RAM, RX_RAM, PCIE2AXI_RAM, AXI2PCIE_RAM Fix looks correct to me on that basis: Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > #define EVENT_DED_TX_RAM_DED_ERR 7 > #define EVENT_DED_RX_RAM_DED_ERR 8 > -#define EVENT_DED_AXI2PCIE_RAM_DED_ERR 9 > -#define EVENT_DED_PCIE2AXI_RAM_DED_ERR 10 > +#define EVENT_DED_PCIE2AXI_RAM_DED_ERR 9 > +#define EVENT_DED_AXI2PCIE_RAM_DED_ERR 10 > #define EVENT_LOCAL_DMA_END_ENGINE_0 11 > #define EVENT_LOCAL_DMA_END_ENGINE_1 12 > #define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13 > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@xxxxxxxxxxxxxxxxxxx > http://lists.infradead.org/mailman/listinfo/linux-riscv
