Hi, On Mon, Nov 21, 2022 at 04:45:48PM -0600, Bjorn Helgaas wrote: > IIUC, the summary is this: > > 00:02.0 bridge window [mem 0x10000000-0x102fffff] to [bus 01-02] > 01:02.0 bridge window [mem 0x10000000-0x100fffff] to [bus 02] > 01:03.0 NIC BAR [mem 0x10200000-0x1021ffff] > 01:04.0 NIC BAR [mem 0x10220000-0x1023ffff] > 02:05.0 NIC BAR [mem 0x10080000-0x1009ffff] > > and it's the same with and without the current patch. > > Are all these assignments done by BIOS, or did Linux update them? > Did we exercise the same "distribute available resources" path as in > the PCIe case? I expect we *should*, because there really shouldn't > be any PCI vs PCIe differences in how resources are handled. This is > why I'm not comfortable with assumptions here that depend on PCIe. > > I can't tell from Jonathan's PCIe case whether we got a working config > from BIOS or not because our logging of bridge windows is kind of > poor. This is ARM64 so there is no "BIOS" involved (something similar though). It is the same "system" that Jonathan used where the regression happened with the multifunction PCIe configuration with the exception that I'm now using PCI devices instead of PCIe as you asked. I'm not 100% sure if the all the same code paths are used here, though.
