Re: [PATCH v3 7/8] arm64: dts: qcom: sm8350: add PCIe devices

[Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>]

On 16/11/2022 16:50, Johan Hovold wrote:
> On Thu, Nov 10, 2022 at 09:31:57PM +0300, Dmitry Baryshkov wrote:
> > Add PCIe0 and PCIe1 (and corresponding PHY) devices found on SM8350
> > platform. The PCIe0 is a 1-lane Gen3 host, PCIe1 is a 2-lane Gen3 host.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> > ---
> >   arch/arm64/boot/dts/qcom/sm8350.dtsi | 246 ++++++++++++++++++++++++++-
> >   1 file changed, 244 insertions(+), 2 deletions(-)
>
> > +		pcie0: pci@1c00000 {
> > +			compatible = "qcom,pcie-sm8350";
> > +			reg = <0 0x01c00000 0 0x3000>,
> > +			      <0 0x60000000 0 0xf1d>,
> > +			      <0 0x60000f20 0 0xa8>,
> > +			      <0 0x60001000 0 0x1000>,
> > +			      <0 0x60100000 0 0x100000>;
> > +			reg-names = "parf", "dbi", "elbi", "atu", "config";
> > +			device_type = "pci";
> > +			linux,pci-domain = <0>;
> > +			bus-range = <0x00 0xff>;
> > +			num-lanes = <1>;
> > +
> > +			#address-cells = <3>;
> > +			#size-cells = <2>;
> > +
> > +			ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
> > +				 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
> > +
> > +			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-names = "msi0", "msi1", "msi2", "msi3",
> > +					  "msi4", "msi5", "msi6", "msi7";
> > +			#interrupt-cells = <1>;
> > +			interrupt-map-mask = <0 0 0 0x7>;
> > +			interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> > +					<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> > +					<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> > +					<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> > +
> > +			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> > +				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> > +				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> > +				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> > +				 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
> > +				 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
> > +				 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
> > +				 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
> > +				 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
> > +			clock-names = "aux",
> > +				      "cfg",
> > +				      "bus_master",
> > +				      "bus_slave",
> > +				      "slave_q2a",
> > +				      "tbu",
> > +				      "ddrss_sf_tbu",
> > +				      "aggre0",
> > +				      "aggre1";
> > +
> > +			iommus = <&apps_smmu 0x1c00 0x7f>;
> > +			iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
> > +				    <0x100 &apps_smmu 0x1c01 0x1>;
> > +
> > +			resets = <&gcc GCC_PCIE_0_BCR>;
> > +			reset-names = "pci";
> > +
> > +			power-domains = <&gcc PCIE_0_GDSC>;
> > +
> > +			phys = <&pcie0_phy>;
> > +			phy-names = "pciephy";
> > +
> > +			perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
> > +			wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
> > +
> > +			pinctrl-names = "default";
> > +			pinctrl-0 = <&pcie0_default_state>;
>
> So I still think these do not belong in the dtsi for the reasons I just
> gave in a reply to v2.

Ack. I must admit, I asked Bjorn and he confirmed that pcie pinconf also 
belongs to the board dtsi. So I think I'll leave the pinctrl-0 here, but 
split the bias/strength to the board dtsi.

I still think that we should agree & document the approach and then 
change all boards to follow it. Otherwise e.g. one of sm8550 review 
comments tells the opposite thing: to move sdcc pinconf to SoC dtsi.

> > +
> > +			status = "disabled";
> > +		};
> > +
> > +		pcie0_phy: phy@1c06000 {
> > +			compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
> > +			reg = <0 0x01c06000 0 0x2000>;
>
> > +			#address-cells = <2>;
> > +			#size-cells = <2>;
> > +			ranges;
>
> These three should not be here (same for pcie1).

Ack

> > +			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> > +				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> > +				 <&gcc GCC_PCIE_0_CLKREF_EN>,
> > +				 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
> > +				 <&gcc GCC_PCIE_0_PIPE_CLK>;
> > +			clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
> > +
> > +			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
> > +			reset-names = "phy";
> > +
> > +			assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
> > +			assigned-clock-rates = <100000000>;
> > +
> > +			#clock-cells = <0>;
> > +			clock-output-names = "pcie_0_pipe_clk";
> > +
> > +			#phy-cells = <0>;
> > +
> > +			status = "disabled";
> > +		};
>
> >   		lpass_ag_noc: interconnect@3c40000 {
> >   			compatible = "qcom,sm8350-lpass-ag-noc";
> >   			reg = <0 0x03c40000 0 0xf080>;
> > @@ -1761,6 +1957,52 @@ tlmm: pinctrl@f100000 {
> >   			gpio-ranges = <&tlmm 0 0 204>;
> >   			wakeup-parent = <&pdc>;
> >   
> > +			pcie0_default_state: pcie0-default-state {
> > +				perst-pins {
> > +					pins = "gpio94";
> > +					function = "gpio";
> > +					drive-strength = <2>;
> > +					bias-pull-down;
> > +				};
> > +
> > +				clkreq-pins {
> > +					pins = "gpio95";
> > +					function = "pcie0_clkreqn";
> > +					drive-strength = <2>;
> > +					bias-pull-up;
> > +				};
> > +
> > +				wake-pins {
> > +					pins = "gpio96";
> > +					function = "gpio";
> > +					drive-strength = <2>;
> > +					bias-pull-up;
> > +				};
> > +			};
> > +
> > +			pcie1_default_state: pcie1-default-state {
> > +				perst-pins {
> > +					pins = "gpio97";
> > +					function = "gpio";
> > +					drive-strength = <2>;
> > +					bias-pull-down;
> > +				};
> > +
> > +				clkreq-pins {
> > +					pins = "gpio98";
> > +					function = "pcie1_clkreqn";
> > +					drive-strength = <2>;
> > +					bias-pull-up;
> > +				};
> > +
> > +				wake-pins {
> > +					pins = "gpio99";
> > +					function = "gpio";
> > +					drive-strength = <2>;
> > +					bias-pull-up;
> > +				};
> > +			};
> > +
> >   			qup_uart3_default_state: qup-uart3-default-state {
> >   				rx-pins {
> >   					pins = "gpio18";
>
> Johan

--
With best wishes
Dmitry