On Thu, Nov 17, 2022 at 05:10:34PM -0600, Bjorn Helgaas wrote: > On Mon, Nov 14, 2022 at 01:59:52PM +0200, Mika Westerberg wrote: > > PCIe switch upstream port may be one of the functions of a multifunction > > device. > > I don't think this is specific to PCIe, is it? Can't we have a > multi-function device where one function is a conventional PCI bridge? > Actually, I don't think "multi-function" is relevant at all -- you > iterate over all the devices on the bus below. For PCIe, that likely > means multiple functions of the same device, but it could be separate > devices in conventional PCI. Yes it can be but I was trying to explain the problem we encountered and that's related to PCIe. I can leave this out if you think it is better that way. > > The resource distribution code does not take this into account > > properly and therefore it expands the upstream port resource windows too > > much, not leaving space for the other functions (in the multifunction > > device) > > I guess the window expansion here is done by adjust_bridge_window()? Yes but the resources are distributed in pci_bus_distribute_available_resources(). > > > and this leads to an issue that Jonathan reported. He runs QEMU > > with the following topoology (QEMU parameters): > > > > -device pcie-root-port,port=0,id=root_port13,chassis=0,slot=2 \ > > -device x3130-upstream,id=sw1,bus=root_port13,multifunction=on \ > > -device e1000,bus=root_port13,addr=0.1 \ > > -device xio3130-downstream,id=fun1,bus=sw1,chassis=0,slot=3 \ > > -device e1000,bus=fun1 > > > > The first e1000 NIC here is another function in the switch upstream > > port. This leads to following errors: > > > > pci 0000:00:04.0: bridge window [mem 0x10200000-0x103fffff] to [bus 02-04] > > pci 0000:02:00.0: bridge window [mem 0x10200000-0x103fffff] to [bus 03-04] > > pci 0000:02:00.1: BAR 0: failed to assign [mem size 0x00020000] > > e1000 0000:02:00.1: can't ioremap BAR 0: [??? 0x00000000 flags 0x0] > > To make sure I have this right: > > 00:04.0 Root Port; makes [mem 0x10200000-0x103fffff] available on bus 02 > 02:00.0 Switch Upstream Port; makes that entire window available on bus 03 > 02:00.1 NIC (nothing left for it) Correct > > > Fix this by taking into account the possible multifunction devices when > > uptream port resources are distributed. > > > > Link: https://lore.kernel.org/linux-pci/20221014124553.0000696f@xxxxxxxxxx/ > > Reported-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx> > > Signed-off-by: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx> > > --- > > The previous version of the series can be found here: > > > > https://lore.kernel.org/linux-pci/20221103103254.30497-1-mika.westerberg@xxxxxxxxxxxxxxx/ > > > > Changes from v1: > > * Re-worded the commit message to hopefully explain the problem > > better > > * Added Link: to the bug report > > * Update the comment according to Bjorn's suggestion > > * Dropped the ->multifunction check > > * Use %#llx in log format. > > > > drivers/pci/setup-bus.c | 56 ++++++++++++++++++++++++++++++++++++++--- > > 1 file changed, 52 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c > > index b4096598dbcb..f3f39aa82dda 100644 > > --- a/drivers/pci/setup-bus.c > > +++ b/drivers/pci/setup-bus.c > > @@ -1830,10 +1830,58 @@ static void pci_bus_distribute_available_resources(struct pci_bus *bus, > > * There is only one bridge on the bus so it gets all available > > * resources which it can then distribute to the possible hotplug > > * bridges below. > > This comment might need to be updated (even if there's only one > bridge, we're going to account for other functions in the > multi-function device). > > But might we not have other devices on the bus even if they're not in > the same multi-function device? What if we had this scenario? > > 00:1f.0 bridge window [mem 0x10200000-0x103fffff] to [bus 04-05] > 04:00.0 bridge to [bus 05] > 04:01.0 NIC [mem size 0x00020000] > 04:02.0 NIC [mem size 0x00020000] > > We can't let 04:00.0 route the entire [mem 0x10200000-0x103fffff] > window to bus 05. Good point. I will update the comment accordingly. > > if (hotplug_bridges + normal_bridges == 1) { > > - dev = list_first_entry(&bus->devices, struct pci_dev, bus_list); > > - if (dev->subordinate) > > - pci_bus_distribute_available_resources(dev->subordinate, > > - add_list, io, mmio, mmio_pref); > > + /* Upstream port must be the first */ > > + bridge = list_first_entry(&bus->devices, struct pci_dev, bus_list); > > + if (!bridge->subordinate) > > + return; > > + > > + /* > > + * It is possible to have switch upstream port as a part of a > > + * multifunction device. For this reason reduce the space > > + * available for distribution by the amount required by the > > + * peers of the upstream port. > > + */ > > + list_for_each_entry(dev, &bus->devices, bus_list) { > > It seems like maybe we ought to do this regardless of how many bridges > there are on the bus. Don't we always want to assign space to devices > on this bus before distributing the leftovers to downstream buses? Yes we do. > E.g., maybe this should be done before the adjust_bridge_window() > calls? With the current code it is clear that we deal with the upstream port. At least in PCIe it is not allowed to have anything else than downstream ports on that internal bus so the only case we would need to do this is the switch upstream port. Let me know if you still want me to move this before adjust_bridge_window() I can do that in v3. Probably needs a comment too.
