> From: Thomas Gleixner <tglx@xxxxxxxxxxxxx> > Sent: Friday, November 11, 2022 9:57 PM > > The new PCI/IMS (Interrupt Message Store) functionality is allowing > hardware vendors to provide implementation specific storage for the MSI > messages. This can be device memory and also host/guest memory, e.g. in > queue memory which is shared with the hardware. > > This requires device specific MSI interrupt domains, which cannot be > achived by expanding the existing PCI/MSI interrupt domain concept which is s/achived/achieved/
