On 11/15/22 1:11 AM, Bjorn Helgaas wrote: > Hi Liu, > > On Mon, Nov 14, 2022 at 03:43:46PM +0800, Liu Peibao wrote: >> The PCI Controller of 2K1000 could not mask devices by setting vender ID or >> device ID in configuration space header as invalid values. > > I don't think this 2K1000 information is really relevant. I > understand that some chipsets might support this, and they might use > that to avoid this issue, but there's no PCI requirement that the > Vendor/Device ID be writable by anything. > OK, I think I got it. >> When there are >> pins shareable between the platform device and the on chip PCI device, if > > What does "pins shareable between the platform device and the on chip > PCI device" mean? > > I assume there's a single device in the hardware, and both the > "platform device" and the PCI device" refer to that single device? > > And there's some reason you prefer to use the platform device > interface to enumerate that device? > No, they are not the same device. For example, GMAC1(on chip PCI device) and GPIO(platform device, not PCI device) 14 use the same pin. The function for this pin can be configured by one bit in general register, eg, 0 for GPIO 14, 1 for GMAC1. Sometimes, GPIO 14 is preferred, so configure the pin with function GPIO 14 and disable GMAC1. >> the platform device is preferred, we should not scan this PCI device. In >> the above scene, add `status = "disabled"` property in DT node of this PCI >> device. >> >> Before this patch, to solve the above problem, we treat the on chip PCI >> devices as platform devices with fixed address assigned by the BIOS. > > This says "before this patch". But the rest of the sentence sounds > like what happens *after* this patch. > In fact, I want to describe an solution. But it seems that I described a little confusing and please check the refactored commit log in the following comments. >> When >> there is device not preferred, add the `status = "disabled"` property in DT >> node. > >> In kernel, the PCI host bridge only scans slot 9/A/B/C/D/E that are >> bridges. > > I guess this has something to do with pdev_may_exist() [1], but why do > you mention it here? Do you intend to remove pdev_may_exist() and use > this DT mechanism instead? > > Bjorn > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pci-loongson.c?id=v6.0#n168 > You are right and I did something ugly in pdev_may_exist() in my kernel. I really don't want to continue doing this, so I am developing this patch. Also I don't want to remove pdev_may_exist(). This patch could replace pdev_may_exist() only in DT, but pdev_may_exist() matters in both ACPI and DT. Overall, how about the following refactored commit log: "This patch adds a mechanism to disable on chip PCI devices by DT. Typically, when there are pins shareable between the platform device and the on chip PCI device, if the PCI device is not preferred, add `status = "disabled"` property to this PCI device DT node. For example, on LS2K1000, GMAC1(on chip PCI device) and GPIO(platform device, not PCI device) 14 share the same pin. If GMAC1 is not preferred, add `status = "disabled"` property in GMAC1 DT node." BR, Peibao
