From: Vidya Sagar <vidyas@xxxxxxxxxx>
Add support for ECAM aperture that is only supported for Tegra234
devices.
Co-developed-by: Vidya Sagar <vidyas@xxxxxxxxxx>
Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx>
Co-developed-by: Jon Hunter <jonathanh@xxxxxxxxxx>
Signed-off-by: Jon Hunter <jonathanh@xxxxxxxxxx>
---
Changes since V1:
- Restricted the ECAM aperture to only Tegra234 devices that support it.
.../bindings/pci/nvidia,tegra194-pcie.yaml | 76 +++++++++++++++----
.../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +-
2 files changed, 62 insertions(+), 16 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
index 75da3e8eecb9..7ae0f37f5364 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
@@ -27,21 +27,12 @@ properties:
- nvidia,tegra234-pcie
reg:
- items:
- - description: controller's application logic registers
- - description: configuration registers
- - description: iATU and DMA registers. This is where the iATU (internal
- Address Translation Unit) registers of the PCIe core are made
- available for software access.
- - description: aperture where the Root Port's own configuration
- registers are available.
+ minItems: 4
+ maxItems: 5
reg-names:
- items:
- - const: appl
- - const: config
- - const: atu_dma
- - const: dbi
+ minItems: 4
+ maxItems: 5
interrupts:
items:
@@ -202,6 +193,60 @@ properties:
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra194-pcie
+ then:
+ properties:
+ reg:
+ minItems: 4
+ maxItems: 4
+ items:
+ - description: controller's application logic registers
+ - description: configuration registers
+ - description: iATU and DMA registers. This is where the iATU (internal
+ Address Translation Unit) registers of the PCIe core are made
+ available for software access.
+ - description: aperture where the Root Port's own configuration
+ registers are available.
+ reg-names:
+ items:
+ - const: appl
+ - const: config
+ - const: atu_dma
+ - const: dbi
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra234-pcie
+ then:
+ properties:
+ reg:
+ minItems: 5
+ maxItems: 5
+ items:
+ - description: controller's application logic registers
+ - description: configuration registers
+ - description: iATU and DMA registers. This is where the iATU (internal
+ Address Translation Unit) registers of the PCIe core are made
+ available for software access.
+ - description: aperture where the Root Port's own configuration
+ registers are available.
+ - description: aperture to access the configuration space through ECAM.
+ reg-names:
+ items:
+ - const: appl
+ - const: config
+ - const: atu_dma
+ - const: dbi
+ - const: ecam
+
unevaluatedProperties: false
@@ -305,8 +350,9 @@ examples:
reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
- <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
- reg-names = "appl", "config", "atu_dma", "dbi";
+ <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
+ reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
#address-cells = <3>;
#size-cells = <2>;
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
index 7287d395e1b6..7e0b015f1414 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
@@ -35,7 +35,7 @@ properties:
maxItems: 5
items:
enum: [ dbi, dbi2, config, atu, atu_dma, app, appl, elbi, mgmt, ctrl,
- parf, cfg, link, ulreg, smu, mpu, apb, phy ]
+ parf, cfg, link, ulreg, smu, mpu, apb, phy, ecam ]
num-lanes:
description: |
--
2.25.1
