On Wed, 09 Nov 2022, Ira Weiny wrote:
Unfortunately the following does not work with the current Qemu.
/*
* NOTE: Currently all the functions which are enabled for CXL require their
* vectors to be in the first 16. Allocate this number as the min/max.
*/
#define CXL_PCI_REQUIRED_VECTORS 16
...
rc = pci_alloc_irq_vectors(pdev, CXL_PCI_REQUIRED_VECTORS,
CXL_PCI_REQUIRED_VECTORS,
PCI_IRQ_MSIX | PCI_IRQ_MSI);
This is because Qemu CXL devices only support (with the event changes I have
made) 8 msg numbers. So the code fails to allocate any vectors.
I guess I should have known better. But allocating something less than 16 I
guess needs to be allowed.
But that also means that beyond knowing _if_ irq's have been enabled I think
each CXL feature needs to know the number of vectors allocated so they can
ensure their msg numbers are going to work.
So how about the following as a diff to this patch?
In the event code I have then used the nr_irq_vecs field to determine if I
should enable the irq for each log.
If you are ok with it I'm going to squash it into your patch and send out a new
version of the event log series.
LGTM, thanks.
