On 11/11/2022 06:37, Thippeswamy Havalige wrote: > Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge > dt binding. > > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@xxxxxxx> > --- > changes in v6: > Added maxItems to clocks property. Where is the rest of the changelog? There were no changes between v1-v6? > > .../bindings/pci/xilinx-nwl-pcie.txt | 73 --------- > .../bindings/pci/xlnx,nwl-pcie.yaml | 149 ++++++++++++++++++ Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
