On 07/11/2022 10:54, Thippeswamy Havalige wrote: > Convert to YAML dtschemas of Xilinx AXI PCIe Root Port Bridge > dt binding. > > Just one blank line before SoB. With commit fixes: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@xxxxxxx> > --- Best regards, Krzysztof