Adding of dditional support to Cadence PCIe controller (i.e. pci-j721e.c) for up to 4x lanes, and reworking of driver to define maximum lanes per board configuration. Changes from v1: * Reworked 'PCI: j721e: Add PCIe 4x lane selection support' to not cause regressions on 1-2x lane platforms Changes from v2: * Correct dev_warn format string from %d to %u since lane count is a unsigned integer * Update CC list Changes from v3: * Use the max_lanes setting per chip for the mask size required since bootloader could have set num_lanes to a higher value that the device tree which would leave in an undefined state * Reorder patches do the previous change to not break bisect * Remove line breaking for dev_warn to allow better grepping and since no strict 80 columns anymore Matt Ranostay (3): PCI: j721e: Add per platform maximum lane settings PCI: j721e: Add PCIe 4x lane selection support PCI: j721e: Add warnings on num-lanes misconfiguration drivers/pci/controller/cadence/pci-j721e.c | 28 ++++++++++++++++++---- 1 file changed, 23 insertions(+), 5 deletions(-) -- 2.38.GIT
