Hello Everyone, this series adds PHY latency properties to the Cadence PCIe driver to improve PTM accuracy, and configures the necessary values for TI's AM64x processors. These latencies are implementation specific and need to be configured in the PCIe IP core's registers to allow the PCIe controller to exactly determine the RX/TX timestamps for PCIe PTM messages. TI doesn't document these values in the datasheet or reference manual as of now, but provided the necessary data via TI's E2E forums (see PATCH 3/3). Best Regards, Dominic Alexander Bahle (3): dt-bindings: PCI: cdns: Add PHY latency properties PCI: cadence: Use DT bindings to set PHY latencies arm64: dts: ti: k3-am64-main: Add latency DT binding .../bindings/pci/cdns,cdns-pcie-ep.yaml | 2 + .../bindings/pci/cdns,cdns-pcie-host.yaml | 2 + .../devicetree/bindings/pci/cdns-pcie-ep.yaml | 20 +++++ .../bindings/pci/cdns-pcie-host.yaml | 20 +++++ arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 4 + .../pci/controller/cadence/pcie-cadence-ep.c | 2 + .../controller/cadence/pcie-cadence-host.c | 1 + drivers/pci/controller/cadence/pcie-cadence.c | 81 +++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 23 ++++++ 9 files changed, 155 insertions(+) base-commit: a185a0995518a3355c8623c95c36aaaae489de10 -- 2.36.0
