On Mon, Sep 26, 2022, Vidya Sagar <vidyas@xxxxxxxxxx> wrote:
>
> commit aeaa0bfe89654 ("PCI: dwc: Move N_FTS setup to common setup")
> incorrectly uses pci->link_gen in deriving the index to the
> n_fts[] array also introducing the issue of accessing beyond the
> boundaries of array for greater than Gen-2 speeds. This change fixes
> that issue.
Dear Vidya,
I am just ok with this patch. By the way, do we need another patch to generalize
this setting? Currently, this code targets only Gen1 and Gen2. But, in
my opinion,
it is possible that this driver can be used for more than Gen2,
later. PCIe Gen6
standard is available and Synopsys has their solution for Gen6. So, would you
send a new patch to generalize this thing, later?
Thank you.
Best regards,
Jingoo Han
>
> Fixes: aeaa0bfe8965 ("PCI: dwc: Move N_FTS setup to common setup")
> Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx>
> Acked-by: Jingoo Han <jingoohan1@xxxxxxxxx>
> ---
> V2:
> * Addressed review comments from Bjorn
> * Added "Acked-by: Jingoo Han <jingoohan1@xxxxxxxxx>"
>
> drivers/pci/controller/dwc/pcie-designware.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 650a7f22f9d0..3df687667f27 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -649,7 +649,7 @@ void dw_pcie_setup(struct dw_pcie *pci)
> if (pci->n_fts[1]) {
> val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> val &= ~PORT_LOGIC_N_FTS_MASK;
> - val |= pci->n_fts[pci->link_gen - 1];
> + val |= pci->n_fts[1];
> dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> }
>
> --
> 2.17.1
>
