From: Xiaochun Lee <lixc17@xxxxxxxxxx>
When enable VMDs on Intel CPUs, VMD controllers(8086:28c0) be
recognized by VMD driver and there are many failed messages of
BAR 13 when scan the bridges and assign IO resource behind it
as listed below, the bridge wants to get 0x6000 as its IO
resource, but there is no IO resources on the host bridge.
VMD host bridge resources:
vmd 0000:e2:00.5: PCI host bridge to bus 10001:00
pci_bus 10001:00: root bus resource [bus 00-1f]
pci_bus 10001:00: root bus resource [mem 0xf4000000-0xf5ffffff]
pci_bus 10001:00: root bus resource [mem 0x29ffff02010-0x29fffffffff 64bit]
pci_bus 10001:00: scanning bus
Read bridge IO resource:
pci 10001:00:02.0: PCI bridge to [bus 01]
pci 10001:00:02.0: bridge window [io 0x1000-0x6fff]
pci 10001:00:03.0: PCI bridge to [bus 02]
pci 10001:00:03.0: bridge window [io 0x1000-0x6fff]
Failed messages of BAR#13:
pci 10001:00:02.0: BAR 13: no space for [io size 0x6000]
pci 10001:00:02.0: BAR 13: failed to assign [io size 0x6000]
pci 10001:00:03.0: BAR 13: no space for [io size 0x6000]
pci 10001:00:03.0: BAR 13: failed to assign [io size 0x6000]
VMD-enabled root ports use
Enhanced Configuration Access Mechanism (ECAM) access
PCI Express configuration space, and offer VMD_CFGBAR as
base of PCI Express configuration space for the bridges
behind it. The configuration space includes IO resources,
but these IO resources are not actually used on X86,
it can result in BAR#13 assign IO resource failed.
Therefor,clear IO resources by setting an IO base value
greater than limit to these bridges here, so in this case,
we can leverage kernel parameter "pci=hpiosize=0KB" to
avoid this failed messages show up.
Signed-off-by: Xiaochun Lee <lixc17@xxxxxxxxxx>
---
drivers/pci/quirks.c | 60 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 4944798e75b5..efecf12e8059 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5956,3 +5956,63 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
#endif
+
+#if defined(CONFIG_X86_64) || defined(CONFIG_X86)
+
+#ifdef CONFIG_UML_X86
+#define is_vmd(bus) false
+#endif /* CONFIG_UML_X86 */
+
+/*
+ * VMD-enabled root ports use Enhanced Configuration Access Mechanism (ECAM)
+ * access PCI Express configuration space, and offer VMD_CFGBAR as the
+ * base of PCI Express configuration space for the bridges behind it.
+ * The configuration space includes IO resources, but these IO
+ * resources are not actually used on X86, and it can result
+ * in BAR#13 assign IO resource failed. Therefor, clear IO resources
+ * by setting an IO base value greater than limit to these bridges here,
+ * so in this case, append kernel parameter "pci=hpiosize=0KB" can avoid
+ * the BAR#13 failed messages show up.
+ */
+static void quirk_vmd_no_iosize(struct pci_dev *bridge)
+{
+ u8 io_base_lo, io_limit_lo;
+ u16 io_low;
+ u32 io_upper16;
+ unsigned long io_mask, base, limit;
+
+ io_mask = PCI_IO_RANGE_MASK;
+ if (bridge->io_window_1k)
+ io_mask = PCI_IO_1K_RANGE_MASK;
+
+ /* VMD Domain */
+ if (is_vmd(bridge->bus) && bridge->is_hotplug_bridge) {
+ pci_read_config_byte(bridge, PCI_IO_BASE, &io_base_lo);
+ pci_read_config_byte(bridge, PCI_IO_LIMIT, &io_limit_lo);
+ base = (io_base_lo & io_mask) << 8;
+ limit = (io_limit_lo & io_mask) << 8;
+ /* if there are defined io ports behind the bridge on x86,
+ * we clear it, since there is only 64KB IO resource on it,
+ * beyond that, hotplug io bridges don't needs IO port resource,
+ * such as NVMes attach on it. So the corresponding range must be
+ * turned off by writing base value greater than limit to the
+ * bridge's base/limit registers.
+ */
+ if (limit >= base) {
+ /* Clear upper 16 bits of I/O base/limit */
+ io_upper16 = 0;
+ /* set base value greater than limit */
+ io_low = 0x00f0;
+
+ /* Temporarily disable the I/O range before updating PCI_IO_BASE */
+ pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
+ /* Update lower 16 bits of I/O base/limit */
+ pci_write_config_word(bridge, PCI_IO_BASE, io_low);
+ /* Update upper 16 bits of I/O base/limit */
+ pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
+ }
+ }
+}
+DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_ANY_ID, PCI_ANY_ID,
+ PCI_CLASS_BRIDGE_PCI, 8, quirk_vmd_no_iosize);
+#endif
--
2.37.3
